Patent
1996-02-12
1997-09-02
Ray, Gopal C.
395856, G06F 1310, G06F 13376
Patent
active
056641680
ABSTRACT:
Method and apparatus in a data processing system (10) for selectively inserting bus cycle idle time. The present invention allows a data processing system (10) to selectively insert a predetermined number of idle clocks at the end of a bus cycle. In one embodiment of the present invention, there is a base register (48) and an option register (46) corresponding to each one of the chip select terminals (73). In one embodiment of the present invention, each option register (46) includes a user programmable idle control bit (110). If a first chip select is used to select a peripheral device during a bus cycle to that same peripheral device, the idle control bit (110) which corresponds to the first chip select determines whether or not one or more idle clocks will be inserted after that bus cycle.
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Motorola, Inc., MC68332 User's Manual, Chapter 4: System Integration Module, pp. 4-27 through 4-46., 1990.
Harwood Ann E.
Le Chinh H.
Yishay Oded
Hill Susan C.
Motorola Inc.
Ray Gopal C.
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