Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-10-23
2001-07-31
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S182000, C345S204000, C345S003100, C348S537000, C348S571000, C331S00100A
Reexamination Certificate
active
06268848
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computer graphics systems. More particularly, this invention relates to a method and apparatus implemented in an automatic sampling phase control system for digital monitors which adjusts the phase of an analog display signal sampling system clock depending upon numerical characteristics of the values of digital samples.
2. Related Art
A computer system may display images on a digital display. Generally, an analog display signal is received by the digital display. The digital display usually samples the analog display signal to generate discrete samples. The discrete samples can be used to determine pixel values which may be used to display images on the digital display.
FIG. 1
shows a portion of a typical computer system including a graphics source
12
and a digital display
14
. The graphic source
12
generates an analog display signal and a corresponding reference signal which are provided to the digital display
14
. The graphics source
12
typically generates the analog display signal by converting a stream of digital image data into an analog signal through a digital to analog converter (DAC)
16
. Control circuitry
18
within the graphics source generates the reference signal which typically includes horizontal synchronization (HSYNC) and vertical synchronization (VSYNC). The analog display signal typically includes RGB (red, blue and green) signal components. Only a single line carrying the RGB signal is shown.
The digital display
14
receives the analog display signal and the reference signal. The digital display
14
includes an analog to digital converter (ADC)
20
which digitally samples the analog display signal. The digital display
12
also includes reference clock source
22
which generates a sampling signal. Ideally, the sampling signal includes a sampling frequency which is equivalent to the rate or frequency that the graphic source
12
clocks image data to the DAC
16
. Typically, the reference clock source
22
is phase locked to the reference signal. The digital display
12
also includes a phase controller
24
which allows adjustment of the phase of the sampling signal. The output of the phase controller
24
is connected to the ADC
20
, and the delayed sampling signal determines the points in time that the ADC
20
samples the analog image signal. Therefore, adjustment of the phase controller adjusts the points in time that the ADC
20
samples the analog image signal. The digital samples generated by the ADC
20
are also received by digital processing and display circuitry
26
.
As shown in
FIG. 1
, the analog display signal and the reference signal are typically coupled between the graphic source
12
and the digital display
14
through separate electrical paths. Due to varying impedances and lengths of the cables, the reference signal and the analog display signal can be received by the digital display
14
at slightly varied times.
Ideally, the output (the analog image signal) of the DAC
16
resembles a stairway, and the ADC
20
samples the analog image signal at the flat areas of the stairway. Also ideally, the flat areas are of sufficient duration in time to allow for some unavoidable phase jitter of the sampling signal. If the flat area of the analog display signal is of substantially greater time duration than the phase jitter of the sampling signal, phase adjustment of the sampling signal is not critical and can normally be performed by a user of the digital display
14
via buttons which control the phase controller
24
.
Traditional digital displays
14
are relatively insensitive to adjustment of the phase of the sampling signal. In many cases, the phase adjustment of the sampling signal is only required to be adjusted a single time. However, with the advent of high resolution flat panels and increasing frame rates of graphic systems, a single adjustment is generally inadequate.
A typical SXGA system includes a 75 HZ refresh rate and a 135 MHZ clock rate (7 nanosecond pixel period). Typically, the duration of the impulse response of the association digital display DAC and cables is 12 to 15 nanoseconds or more. This means that the flat area of the DAC output is missing altogether and the adjustment of the phase of the sampling signal becomes critical. Incorrect selection of the phase delay of the sampling signal diminishes the resolution of the digital display
14
. Fine image features appear fuzzy and noise-like artifacts may be introduced because the sampling of the analog image signal is extremely sensitive to phase jitter of the delayed sampling signal.
FIG. 2
shows amplitude versus time response of a single pixel of an analog display signal for a high performance digital display
14
. The signal is a pulse, which represents a single pixel having a high intensity, in which neighboring pixels on either side have a low intensity. The pulse is narrow, has tilted edges, and does not have a flat top. Clearly, deviations in the point in time at which the pulse of the analog image signal is sampled, introduces great variations in the magnitude of the sampled digital data.
As indicated in
FIG. 2
, the optimal sampling point is at the analog signal peak
210
of the pulse for a single pixel. Sampling the pulse earlier at point
212
, or later at point
214
provides a digital data representation of the pixel which is lower in magnitude than the digital data representation provided when sampling at the peak.
It is desirable to have a method and apparatus of a computer digital display which provides automatic adjustment of a sampling clock which provides optimal sampling of an analog display signal.
SUMMARY OF THE INVENTION
The present invention is directed to a computer digital display which provides for optimal automatic sampling of an analog display signal. As described in further detail below, the invention takes advantage of the property of common image frames, which do not change substantially in a short duration.
Assuming first for illustration only, that successive image frames (and thus the analog signal portions for a particular pixel position) do not change in content, the sampling phase can be varied to maximize the digital sample for a pixel position. However, the assumption that the analog signal for the pixel position is not changing in successive frames may not hold true.
Accordingly, the present invention generates a value which is a function of several digital samples (corresponding to several pixel positions) of an image frame, and varies the sampling phase to maximize the value. Assuming the changes between several successive frames are minimal (or non-existent), sampling with the proper phase results in maximum value for the function. Therefore, the sampling phase is varied to maximize the function value. However, if the successive image frames are changing substantially in content, phase adjustment is inhibited or prevented.
Several approaches may be employed in accordance with the present invention for determining which pixel positions are selected and for varying the sampling phase. In a first embodiment, a first step of the method includes sampling a plurality of lines of the analog display signal at points in time determined by the delayed sampling clock. A second step includes detecting peaks and valleys of a signal representing the digital signal digital samples.
A third step includes generating a first numerical value based upon relative values of magnitudes of the peaks and valleys. A fourth step includes adjusting the delay of the sampling clock maximizing the first numerical value.
A second embodiment of the invention is similar to the first embodiment. The second embodiment further includes generating a second numerical value based on values of first pixels of lines of the display signal digital samples, and adjusting the delay of the sampling clock maximizing the second numerical value.
A third embodiment of the invention is similar to the second embodiment. The third embodiment further includes summing a wei
Genesis Microchip Corp.
Hjerpe Richard
Law Firm of Naren Thappeta
Zamani Ali A.
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