Method and apparatus for writing to memory components

Static information storage and retrieval – Addressing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36523004, 36523008, 3652385, G11C 14401

Patent

active

058448551

ABSTRACT:
Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

REFERENCES:
patent: 4727363 (1988-02-01), Ishii
patent: 4823119 (1989-04-01), Ishii
patent: 4899310 (1990-02-01), Baba et al.
patent: 4912658 (1990-03-01), Sfarti et al.
patent: 4999620 (1991-03-01), Ishii
patent: 5109348 (1992-04-01), Pfeiffer et al.
patent: 5134589 (1992-07-01), Hamano
patent: 5148396 (1992-09-01), Nakada
patent: 5282177 (1994-01-01), McLaury
patent: 5319606 (1994-06-01), Bowen et al.
patent: 5680361 (1997-10-01), Wane et al.
Patent Abstracts of Japan, vol. 12, No. 43 (P-664) & JP,A,62 191 971 (Feb. 9, 1988).
Patent Abstracts of Japan, vol. 12, No. 307 (P-747) & JP,A,63 076 195 (Aug. 22, 1988).
Patent Abstracts of Japan, vol. 16, No. 252 (P-1367) & JP,A,04 060 586 (Jun. 9, 1992).
International Preliminary Examining Authority, PCT International Preliminary Examination Report, dated Aug. 24, 1995 for PCT application no. PCT/US94/06157.
International Preliminary Examining Authority, PCT International Preliminary Examination Report, dated May 12, 1995 for PCT application no. PCT/US94/06157.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for writing to memory components does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for writing to memory components, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for writing to memory components will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2400907

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.