Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-07-06
1997-07-22
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518508, 36518529, G11C 1134
Patent
active
056509677
ABSTRACT:
A DRAM-compatible nonvolatile memory includes a FLASH memory and a logic controller. The logical controller accepts conventional DRAM command protocol and accepts data and addresses from DRAM data and address buses, respectively. The logic controller responds to repeated CAS-before-RAS signals and a write enable signal to initiate block erases and writes to the FLASH memory. The nonvolatile, DRAM-compatible memory is incorporated in a package having the same pin structure as a conventional DRAM package, such that the nonvolatile, DRAM-compatible memory can be mounted in a DRAM mount, such as a socket. Because the nonvolatile, DRAM-compatible memory can share common data, address, and command lines with conventional DRAMs, a single memory card can be produced containing both conventional DRAMs and the nonvolatile, DRAM-compatible memories.
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Intel, Advance Information, 28F016XD, 16-mbit (1Mbit.times.16) DRAM-Interface Flash Memory, Order No. 290533-001, Intel Corporation, Oct. 1994, pp. 1-55.
Micro)n Technology, Inc.
Nelms David C.
Tran Michael T.
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