Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-07-29
2000-06-13
Phan, Trong
Static information storage and retrieval
Floating gate
Particular biasing
36518529, 365218, G11C 1606, G11C 1604, G11C 700
Patent
active
060757272
ABSTRACT:
A method for writing to a bit of a non-volatile memory (50) by alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). Upon completion of the write operation a verify erase (VE) indication and a verify program (VP) indication are provided to a memory controller (58), which then determines if multiple cycles are necessary. The configuration of the memory cell allows isolation of each bit in the memory array to avoid effects of writes to neighbor bits. According to one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete.
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Bron Michel
Marquot Alexis
Morton Bruce Lee
Stout Graham
Clingan Jr. James L.
Motorola Inc
Phan Trong
LandOfFree
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