Semiconductor device manufacturing: process – Forming schottky junction
Reexamination Certificate
2000-03-31
2002-03-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming schottky junction
C438S630000, C438S680000, C438S683000, C438S603000
Reexamination Certificate
active
06355545
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus for wiring, a wire and an integrated circuit. In particular, the invention relates to, for example, a method and an apparatus for wiring whose material is plugged sufficiently so as to prevent generation of a void or to prevent disconnection, a wire and an integrated circuit having the wire.
2. Description of the Related Art
Recently, semiconductor devices have been integrated so highly that a designing rule of nanometer level has been applied to a design of integrated semiconductor devices instead of the designing rule of micron level (e.g., The National Technology Roadmap for Semiconductors Technology Needs, SIA, 1997 edition). A multi-layered wiring structure including wires made on each layer of multiple layers has been utilized to integrate semiconductor devices. An electric interconnection among these wires made on the multiple layers inserting an interlayer dielectronics is connected by plugging conductive material into a hole (hereinafter, referred to as “a via hole”) produced in the dielectronics. This is called as a plugged wiring (also called as “a vertical wiring”, hereinafter). Here, the via hole includes a contact hole and a via hole.
To produce the above vertical wiring, a thin film deposition technique is utilized such as physical vapor deposition method (PVD method) or chemical vapor deposition method (CVD method). The PVD method is roughly explained by the following: first, plasma is made from argon gas, etc., and voltage is impressed to the plasma to accelerate. The accelerated Ar ion comes into collision with target material, and then atoms come out of the target material to be plugged (This is so-called sputtering). Plugging is performed by adsorbing atoms come out of the target material to the via hole. The CVD method is simply described as the method of forming a thin film made from precursors supplied as gas by chemical reaction on the surface of a substrate film.
These years, shrink of devices has been done to make highly integrated devices. And small feature of multilevel interconnects (=wire) have made progress to draw maximum capacity according to the shrink. Because of shrink of the wire and unchanged thickness of dielectrics layer, a ratio of vertical and/or lateral size of interconnects including dielectrics must be changed. Therefore, as compared with a conventional via hole, a ratio of depth and diameter (aspect ratio) is changed. Namely, the aspect ratio becomes large according to the shrink. For example, in case of 4 G bit DRAM, the aspect ratio becomes 6 through 8 at maximum.
There is a problem that it is difficult to plug the wiring material sufficiently into the via hole having a large aspect ratio using the conventional PVD method or CVD method.
FIG. 7
shows a void formation generated by insufficient deposition method. In
FIG. 7
, a via hole
10
is provided for an electric interconnection between a wire A and a wire B through dielectronics C. Accordingly, it is desired that wiring material
101
is plugged into the via hole
10
with no voids. However, the conventional plugging method does not work sufficiently, which causes to generate a void
102
. This may further cause a problem to increase interconnect resistance or in a worse case, to generate disconnection. The problem is brought by poor stepcoverage, i.e., a metal film is made nonuniformly on the side surface of the via hole
10
at an initial stage of deposition. In a worse case, the metal film is not made on the side surface of the via hole
10
.
Stepcoverage depends on “wettability” between an atom or a molecule of the surface of the via hole
10
and an atom or a molecule of the wiring material to be plugged whether it is possible to plug the wiring material sufficiently into the via hole
10
without generating a void. Accordingly, the surface of the via hole is generally improved so as to have good wettability. A very thin metal film consisting of the wiring material is formed to be used for an initial growth surface. This method provides the same effect as improvement of the surface. In this case, the thin metal film is called “Wetting layer”. Namely, the wetting layer is formed to plug the wiring material sufficiently afterwards. The above “wettability” is determined based on chemical affinity of the surface of solid.
However, when the wetting layer having good wettability is formed nonuniformly on the side surface of the via hole
10
, it is difficult to plug the wiring material sufficiently. As a result, the void
102
is generated. This is because the PVD method cannot plug the wiring material sufficiently because of geometric reason. When the CVD method is applied to the wetting layer formed nonuniformly, it occurs a difference in the speed of forming film according to nonuniformity of the wetting layer. This is because the speed of forming film is relatively proportional to the density of the wetting layer formed on the surface. Accordingly, the wiring material is formed better at a region having higher speed of forming film. As a result, the via hole
10
is closed, which prevents the wiring material from being supplied inside of the via hole. Therefore, the wiring material cannot be plugged sufficiently.
As has been described, it is impossible to plug the wiring material sufficiently using the conventional plugging method. Therefore, there is a problem to generate a void, which causes to increase interconnect resistance, and in a worse case, to generate disconnection.
The present invention is provided to solve the above problems of the conventional methods. The invention aims, for example, to prevent increase of the interconnect resistance or disconnection due to the generation of a void by forming the initial growth surface (wetting layer) uniformly and plugging the wiring material sufficiently.
Further, the invention aims to improve the reliability of conductibility in the wire by preventing increase of the interconnect resistance or disconnection due to the generation of a void.
Yet further, the invention aims to provide a reliable plugged wiring (vertical wiring) to draw capacity of an integrated circuit comprising high-integrated semiconductor devices.
SUMMARY OF THE INVENTION
The main object of the invention is, for example, to make the initial growth surface (wetting layer) uniformly on the surface of the via hole. To make the initial growth surface uniformly, however, a substrate on which the initial growth surface is made should be produced uniformly. Accordingly, to make the initial growth surface uniformly requires to produce the substrate uniformly at a previous stage of the forming step of initial growth surface. The present invention is directed to this requirement.
According to the present invention, a method for wiring includes a step of treating a surface of a via hole produced in dielectronics to provide the surface with chemical affinity, and a step of plugging wiring material into the via hole having the surface treated.
Further, according to another aspect of the present invention, an apparatus for wiring includes a surface treatment unit for treating a surface of a via hole produced in dielectronics to provide the surface with chemical affinity; and a plug unit for plugging wiring material into the via hole having the surface treated.
Further, according to another aspect of the present invention, a wire includes dielectronics having a via hole whose surface has been treated to have chemical affinity; and wiring material plugged into the via hole.
Yet further, according to another aspect of the present invention, an integrated circuit having a plurality of semiconductor devices, a plurality of wires for connecting electrically the plurality of semiconductor devices and located in respective layers of a plurality of layers having an interlayer consisting of dielectronics, and a vertical wiring for connecting electrically the plurality of wires located in the plurality of layers having the interlayer consisting of dielectron
Anya Igwe U.
Semiconductor Leading Edge Technologies Inc.
LandOfFree
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