Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-03-23
2001-12-18
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C714S733000
Reexamination Certificate
active
06331782
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention pertains to testing microelectronic circuits such as semiconductor integrated circuits.
Electronic circuits, including semiconductor integrated microelectronic circuits, are tested during and after the manufacturing process. Testing verifies that the circuit has been accurately fabricated and is functioning properly.
Test circuits are sometimes included in the design of an integrated circuit. These test circuits are designed to generate particular responses to known inputs. In addition, test points are established in the circuit at which signals in the circuit may be monitored during testing.
Electrical paths are provided to the test circuits and to the test points so that the signals to be monitored may be detected. In addition, in certain circumstances, the tester may be required to supply specific known test inputs to the test circuit or to a particular point in the circuit so that a particular function may be tested.
Each of these input paths and output paths generally requires a contact point at which external test apparatus may be connected. Each such contact point includes a pad on the integrated circuit to which a test probe may be attached (for testing at the die stage), and an external pin (for testing after packaging).
A conductive path, or trace, is designed into the integrated circuit to conduct the signal to be observed from the point on the circuit on which it is generated to a point at which a contact pad and/or pin can be provided. Generally these contact pads are placed at the perimeter of the integrated circuit. A trace also may be necessary to provide a path for an input test signal from a contact pad to a particular point in the circuit.
Contact points such as pads on the integrated circuit or pins in the packaged device for device testability are readily available when the tester is required only to test the overall device by supplying input signals to the regular device input, and by observing the output signals at the regular device output. The tester can simply contact the regular signal input and output points of the device to perform such a test. However, the tester may be required to observe a point other than the regular device input and output. Each additional point to which test contact is desired requires an additional contact pad and pin, and an additional trace from the circuit point to be observed to the contact pad.
The additional contact point or points, and the traces from the contact points to the circuit points to be tested, complicate the design of integrated circuits. Sometimes the designer is forced to decide between testability and efficient design. For example, there may not be sufficient room for an additional contact pad on the integrated circuit to provide a test contact. Or, there may not be an available pin on the package. In other circumstances, a conductive trace from a point in the circuit to a contact pad may interfere with other aspects of the circuit design.
Once testing of the microelectronic device is completed, the test circuit and the electrical connections to the test circuit usually have no useful function. However, they continue to occupy space in the device. On the integrated circuit, the pads for the input and output pins for the test circuit consume valuable chip “real estate.” In addition, physical size often limits the number of input and output pins that may be included on a packaged chip. Pins on the packaged device needed only for testing may displace pins that could be used for other purposes related to the operation of the integrated circuit for its intended purpose by its ultimate user.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved system for testing electronic circuits.
It is an object of the present invention to provide an integrated circuit having improved testability.
It is an object of the present invention to provide an improved method of testing microelectronic circuits.
It is an object of present invention to provide a method of testing electronic circuits using a minimum of space on the circuit.
It is an object of the present invention to provide an apparatus for, and a method of, testing an integrated circuit without requiring special test contact pads on the integrated circuit.
It is an object of the present invention to provide improved testability of microelectronic devices without requiring extra input and output pins.
It is an object of the present invention to provide the ability to probe an internal test point in a microelectronic device.
A system for testing a microelectronic circuit in accordance with the invention includes a test bed for mounting a microelectronic circuit, and a signal source for applying a signal to a microelectronic circuit mounted on the test bed.
The test system additionally includes a test probe for receiving electromagnetic response signals from the microelectronic circuit mounted on the test bed. In a referred form, the electromagnetic response signals are radio-frequency signals. The test system additionally includes a computer connected to the test probe for analyzing the received signals.
An integrated circuit constructed for testability in accordance with the invention includes a test circuit portion that emits electromagnetic radiation in response to a predetermined signal applied to the test circuit.
A combination of an integrated circuit and an apparatus for testing that integrated circuit may be constructed in accordance with the invention. The combination includes an integrated circuit incorporating a test circuit portion. The test circuit portion of the integrated circuit is configured so that as a first electrical effect is generated in the test circuit portion the test circuit portion emits electromagnetic radiation. The test device of the combination includes an electromagnetic radiation receiver for detecting electromagnetic radiation emitted by the test circuit portion of the integrated circuit, and an analyzer for analyzing the electromagnetic radiation detected by the receiver.
A method of testing a semiconductor integrated circuit in accordance with the invention includes applying a predetermined signal to the integrated circuit to cause the integrated circuit to emit electromagnetic radiation. An electromagnetic receiver detects the electromagnetic radiation emitted by the integrated circuit. The electromagnetic radiation detected by the receiver is analyzed by a computer analyzer.
REFERENCES:
patent: 5218294 (1993-06-01), Soiferman
patent: 5270655 (1993-12-01), Tomita
patent: 5569993 (1996-10-01), Keith
patent: 5570035 (1996-10-01), Dukes et al.
patent: 5764655 (1998-06-01), Kirihata et al.
patent: 0 805 356 A2 (1997-11-01), None
patent: 10026647 (1998-01-01), None
patent: WO 99/32893 (1999-07-01), None
“Contactless Function Test of Integrated Circuits on the Wafer”, by H.H. Berger et al., taken from the Proceedings of the 22nd International Symposium for Testing and Failure Analysis, Nov. 18-22, 1996, pp. 263-264.
Andrews, Jr. Warner B.
Hale Kelly H.
Henderson P. Michael
Johnston James W.
Siann Jonathan I.
Conexant Systems Inc.
Karlsen Ernest
Snell & Wilmer L.L.P.
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