Electrical transmission or interconnection systems – Plural load circuit systems
Reexamination Certificate
2000-03-30
2001-05-29
Riley, Shawn (Department: 2838)
Electrical transmission or interconnection systems
Plural load circuit systems
C307S033000, C323S224000, C323S274000, C363S016000, C363S131000
Reexamination Certificate
active
06239509
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to DC—DC switched mode power converters. More particularly, the present invention is directed to a method and apparatus for regulating in a transformer-coupled power supply the output of a secondary stage by controlling the primary output.
2. The Background
Switched mode DC—DC power converters are common in the electronics industry. They are frequently used to convert one available DC level voltage to another DC level voltage, often needed for a particular set of semiconductor chips. Such power converters generally use one or more electrically controlled switches (such as N- or P-Channel MOSFETs) the gates of which are controlled by a switched mode power supply controller circuit which is often integrated onto a single chip.
As electronic devices become faster, smaller and more portable, the need for increased electrical efficiency in DC-DC converters used in these devices is becoming more important. Energy wasted in portable electronics devices prematurely drains the battery powering the device and creates waste heat which must be managed. Relatively small increases in overall electrical efficiency such as from 75% to 85%—result in a major decrease in wasted power and waste heat—e.g., from 25% to 15%. One of the methods commonly used to save power, particularly in portable devices, is to interrupt the operation of a switched mode power supply when there is a low current demand from the supply, and restart the power supply when current demand resumes.
Turning now to
FIG. 1
, a transformer-coupled step-down power supply or converter is shown schematically. Switches S
1
and S
2
control the voltage at the phase node, Ø. When S
1
is on, the phase node, Ø, is at VIN
1
(a first input voltage). When S
2
is on, the phase node, Ø, is at ground,
10
(a second input voltage). This type of converter is known as a synchronous pulse width modulation (PWM) converter.
The output filter (here, capacitor C
1
) averages the voltage at the phase node, Ø, to generate VOUT
1
, which is typically a DC level voltage.
FIG. 2
illustrates the switching waveforms for the circuit of FIG.
1
. The waveform for SS
1
(switching signal
1
controlling S
1
) is essentially 180 degrees out of phase with the waveform of SS
2
(switching signal
2
controlling S
2
). It is usually turned off slightly before SS
2
activates to prevent a short circuit or cross conduction condition. Vpri switches between VIN
1
−VOUT
1
and −VOUT
1
following the SS
1
signal. Vpri is the voltage across the primary of transformer T
1
. Vsec is the voltage across the secondary or output winding of T
1
and it is simply the turns ratio (Nsec/Npri) multiplied by Vpri. VOUT
1
is filtered by capacitor C
1
and thus ramps up when Vpri is available and ramps down when it is not. VOUT
2
is powered by the output of the secondary winding of T
1
as rectified by diode D
1
. It is filtered by capacitor C
2
. Many other configurations of this basic idea are known to those of skill in the art for providing various output voltages, as desired.
It is common practice for modern switched mode power supplies used in battery operated equipment or other applications where efficiency and power saving capabilities are paramount to utilize various switching modes in order to optimize the efficiency of the power supply over a wide range of load currents. The switched mode power supply will typically operate at a fixed frequency to allow easy selection of output filter components, but as the load current is reduced, the converter will enter a “power save” mode which drops switching cycles, conserving the gate charge energy associated with switching the power bridge. If a transformer coupled output stage is used, the secondary output is unregulated when the primary stops switching in power save mode. Since the careful regulation of the secondary output voltage can be critical in some applications, this poses a problem.
Turning to
FIG. 3
, a circuit known in the art which uses one method to solve the problem of loss of secondary regulation in a power supply is shown. In the circuit shown in
FIG. 3
the output of the secondary winding
12
of transformer T
1
is used with the rectifying function of diode D
1
to generate the input voltage to a conventional linear regulator
14
having, for example, an IN terminal for connection to a power supply voltage such as VOUT
2
, a REF terminal for connection to a source of a reference voltage, a REG output terminal for output of a regulated voltage level and a FB feedback input terminal for connection to the is regulated output voltage level, such as VOUT
3
, for sensing that voltage level.
A current sense device, such as resistor Rcs, is used to determine the primary supply output current. Note that many ways of sensing current are known. In the embodiment shown in
FIG. 3
, Rcs is connected between the terminals of Op Amp
22
to provide an output signal on line
24
to control circuitry
16
. When the primary supply output current drops below a predetermined level, the control circuitry
16
stops issuing signals SS
1
and SS
2
which, in turn, stops switching switches S
1
and S
2
. Under these conditions, when the linear regulator output VOUT
3
is heavily loaded, the secondary output VOUT
2
will droop. Comparator AR
1
compares VOUT
2
with a predetermined reference level “REF”. When the droop is sufficient that VOUT
2
drops below REF, a single primary side switching cycle is generated. The first event is typically to turn on the synchronous switch S
2
for a fixed period of time by generating a pulse with a one shot device
18
which is, in turn, connected to one input of an OR gate
20
. The other input of OR gate
20
is connected to SS
2
. This allows the primary control loop to bypass its power save mode circuitry, which would turn the primary switcher off under normal conditions due to the light load on the primary.
Turning on S
2
transfers energy from the primary output capacitor C
1
to the secondary output capacitor C
2
. Comparator AR
1
monitors the rising input voltage VOUT
2
to the linear regulator
14
with the hysteresis of the comparator determining the level to which VOUT
2
is raised. When the secondary output voltage VOUT
2
is pumped up and detected by comparator AR
1
, the secondary regulation signal becomes inactive and the primary control loop returns to the power save mode, dropping switching signals when possible in order to improve efficiency. So when comparator AR
1
decides that the voltage droop on VOUT
2
is too much, a single pulse is generated to cause the switcher to execute one cycle, recharging the capacitor filters and reducing the droop. Comparator AR
1
will continue to cause pulses to be generated for so long as VOUT
2
is below REF.
Another prior circuit applies one or more pulses to the S
2
and/or S
1
switches and uses a comparator to sense droop on VOUT
2
to determine when to stop sending the pulses. During this time the power supply does not reenter synchronous conduction mode where the switching of S
1
and S
2
is complementary.
SUMMARY OF THE INVENTION
A step-down switched-mode power supply circuit includes a transformer having at least one primary winding and at least one secondary winding, a current sensing device for sensing a current through a primary winding of the transformer, a first switch and a second switch, a first comparator for determining if the current through the current sensing device exceeds a threshold, a voltage regulator coupled to the secondary winding to produce a regulated voltage, a second comparator for determining if the regulated voltage has drooped below an acceptable level, a counter coupled to the second comparator for generating a signal having a fixed number of switch cycles, and control circuitry for generating signals controlling the first switch and the second switch and responsive to the first comparator to enter a power saving mode disabling the signals, and to the second comparator to temporarily exit the power
Fogg John
Rader, III William Edward
Riley Shawn
Ritchie David B.
Semtech Corporation
Thelen Reid & Priest LLP
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