Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-06-12
2004-06-15
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S260000
Reexamination Certificate
active
06750712
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data signaling devices, and more particularly, to methods and apparatuses for optimizing gain in differential feedback amplifiers using clamping resistors.
BACKGROUND OF THE INVENTION
Differential feedback amplifiers are used in a variety of high-gain high-speed a applications.
FIG. 1
illustrates an example application in optical communications where conventional differential feedback amplifiers
102
are used to implement a limiting amplifier
110
that amplifies the output of a trans-impedance amplifier
104
, the trans-imnpedance amplifier providing a differential voltage output in correspondence with the current output of a photodiode
106
, for example. The output of the limiting amplifier can be a differential data signal representing a received optical data signal that conforms with signaling standards such as LVDS or CML, for example. Such an output can then be supplied to other electronic circuits for further processing, for example.
In these and other applications for differential feedback amplifiers
102
, particularly high speed applications in excess of 1 Gbps in a limiting amplifier example, it is desired that amplifiers
102
provide high gain so as to insure a rapid change in output in response to a small and high frequency change in received input. However, this usually requires the output of the amplifiers
102
to be clamped so that the high gain does not cause the output to saturate the subsequent stage amplifier(s)
102
.
FIG. 2A
more fully illustrates an example implementation of differential feedback amplifier
102
in accordance with the prior art. As shown in
FIG. 2A
, differential inputs IN+ and IN− are provided to transistors Q
1
and Q
2
, respectively, and are used to provide amplified differential outputs OUT+ and OUT−. In this example implementation, the open-loop, small-signal gain A
v
is provided by transistors Q
1
and Q
2
, and is controlled by resistors RL. More particularly, the gain A
v
is proportional to IBIAS×RL. To complete the correspondence between
FIGS. 1 and 2A
, buffer transistors QBUF and current sources IOUT are shown for providing the proper levels for VOUT− and VOUT+. However, these components will not be shown in subsequent drawings for clarity of the invention.
In operation, depending on a difference between inputs IN+ or IN−, either Q
1
or Q
2
will be caused to draw more (or less) current from common current source BIAS to flow through a conduction path including that transistor. The different amounts of current drawn in each conduction path causes a voltage differential between output nodes OUT+ and OUT− due to the different voltage drops between the identical resistances RL in the different conduction paths including Q
1
and Q
2
.
The open-loop gain A
v
is determined in accordance with IBIAS×RL and needs to be high to allow the feedback to work properly through feedback resistors RFB so that the closed-loop gain of the circuit can be set predominantly by the values of RFB, as it should be. By increasing the resistance of RL, one can increase the gain A
v
towards the desired amount. (It should be noted that this can also be done by increasing the bias current IBIAS, but this alternative is not preferred because it leads to increased power consumption.) However, as RL is increased, the voltage drop between the collector of transistors Q
1
and Q
2
and the voltage source Vdd increases, causing the voltage at the collector of transistors Q
1
and Q
2
to fall closer to the voltage at the base, and causing Q
1
and Q
2
to go into saturation and lose their current gain. Accordingly, RL (and hence, the gain A
v
) must be limited to permit Q
1
and Q
2
to remain optimally operational.
One conventional way to address this problem, as well as the saturation problem referred to above, is to clamp the outputs OUT+ and OUT−. This conventional approach is illustrated in FIG.
2
B. As shown in
FIG. 2B
, differential feedback amplifier
102
further includes clamping diodes D
1
and D
2
arranged in a symmetrical back-to-back configuration between nodes OUT+ and OUT−. Such an arrangement insures that the differential voltage between OUT+and OUT− (and hence the maximum offset from a common mode voltage at either node) will never exceed the differential amount of voltage across D
1
and D
2
required to make either conduct, without having to reduce RL (and hence, the gain A
v
).
The conventional approach described above has drawbacks, however. For example, in many processes, the voltage differential between nodes OUT+ and OUT− must be at least 600-700 mV for the diodes to have any effect. However, many small signal applications (e.g. LVDS or CML) usually only have a differential of about 350 mV. Accordingly, most conventional diodes are useless in such applications. Although Schottky diodes require only about a 200-400 mV differential to be useful, they are difficult to implement in many processes because of yield and cost issues and therefore fail to provide an effective solution to the conventional approach.
SUMMARY OF THE INVENTION
The present invention relates to data signaling apparatuses and methods. According to one aspect of the invention, a data signaling apparatus includes a differential amplifier for providing an amplified differential output on a pair of outputs in response to a differential signal provided on a pair of inputs, and a clamping resistor between the pair of inputs. The clamping resistor acts to effectively reduce the swing in differential inputs, thereby allowing a reasonably high gain that does not result in problematic differential outputs. Further, since the resistor is operative for all voltage ranges, it is useful in small signal applications where diodes cannot be used or are too difficult to implement. The invention is particularly useful in high-gain limiting amplifiers for high-speed applications in excess of 1 Gbps. According to another aspect of the invention, a data signaling method includes receiving a differential signal on a pair of inputs, reducing the magnitude of the differential signal by a scale factor using a clamping resistor across the pair of inputs, and providing an amplified differential output on a pair of outputs in response to the scaled differential signal provided on the pair of inputs.
REFERENCES:
patent: 4161693 (1979-07-01), Carlson
patent: 4437123 (1984-03-01), Harlan
patent: 4473804 (1984-09-01), Wahlquist
patent: 5955918 (1999-09-01), Uno
patent: 6028464 (2000-02-01), Bremner
Artisan Components Inc.
Mottola Steven J.
LandOfFree
Method and apparatus for voltage clamping in feedback... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for voltage clamping in feedback..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for voltage clamping in feedback... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3364486