Method and apparatus for visual verification of proper assembly

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428209, 428901, 174250, B32B 900

Patent

active

052663809

ABSTRACT:
A printed circuit (pc) board (105) having at least two layers, wherein proper assembly and alignment of the at least two layers may be visually verified, comprises a first layer (410) having a first printed circuit pattern (305) formed thereon, the first printed circuit pattern (305) including a first identifier (115) formed along at least one edge (405) of the first layer (410). The pc board (105) further comprises a second layer (420) having a second printed circuit pattern (305) formed thereon, the second printed circuit pattern (305) including a second identifier (120) formed along at least one edge (405) of the second layer (420), the second identifier (120) being visibly aligned with the first identifier (115) in a predetermined alignment to indicate that the first layer (410) and the second layer (420) are correctly laminated.

REFERENCES:
patent: 4243474 (1981-01-01), Shirai et al.
patent: 4810563 (1989-03-01), DeGree et al.

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