Electricity: power supply or regulation systems – In shunt with source or load – Using a three or more terminal semiconductive device
Reexamination Certificate
2000-07-20
2002-04-23
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using a three or more terminal semiconductive device
C323S288000, C323S290000
Reexamination Certificate
active
06377032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to DC-DC switched mode power converters. More particularly, the present invention is directed to a method and apparatus for providing virtual current sensing capabilities in DC-DC switched mode power converters.
2. The Background
Switched mode DC-DC power converters are common in the electronics industry. They are frequently used to convert one available DC level voltage to another DC level voltage, often needed for a particular set of semiconductor chips. Such power converters generally use one or more electrically controlled switches (such as N- or P-Channel MOSFETs), the gates of which are controlled by a switched mode power supply controller circuit which is often integrated onto a single chip.
A typical synchronous DC-DC pulse-width modulated (“PWM”) converter
100
in a step-down buck converter configuration is shown in
FIG. 1. A
drive signal D generated within control circuitry
110
is routed to drive logic
115
, which generates the HI and LO signals. The controller drive logic
115
modulates the HI and LO signals to alternatively turn ON and turn OFF the output transistor switches, M
UPPER
and M
LOWER
in switch block
120
. This alternate turning ON and OFF of the switches creates a square wave on the SW node, whose duty cycle is equal to (V
OUT
/V
IN
). Switches M
UPPER
and M
LOWER
control the voltage at the phase node, SW. When M
UPPER
is on, the phase node, SW, is at V
IN
(a first input voltage). When M
LOWER
is on, the phase node, SW, is at ground,
130
(a second input voltage).
In the context of the present invention, duty cycle is defined as the ON-time (or pulse width) of a pulse divided by the period of that waveform. As those of ordinary skill in the art will recognize, the square wave on the SW node is averaged by the output filter made up of inductor L
OUT
and capacitor C
OUT
to produce an output voltage determined by the expression V
OUT
=V
FB
*(1+(R
1
/R
2
)). Ideally, the converter is intended to provide output current up to some preset limit with no change in output voltage. As is well known to those of ordinary skill in the art, the current sense resistor, R
SENSE
, is traditionally used to obtain a voltage V
Rsense
=(I
L
*R
SENSE
), where I
L
is the current through the inductor L
OUT
. The voltage across the current sense resistor R
SENSE
is reported to the control circuitry
110
via the CSH (“current sense high”) and CSL (“current sense low”) signals. Also, the output voltage V
OUT
is reported to control circuitry
110
via the CSL signal and the FB signal, which is derived from the voltage divider network formed by resistors R
1
and R
2
. Additional details necessary for practically implementing typical control circuitry
110
are well known to those of ordinary skill in the art, and are not discussed in further detail herein so as not to overcomplicate the present disclosure.
Still referring to
FIG. 1
, the shape of the voltage waveform across R
SENSE
is triangular, where the rising slope can be expressed as follows:
rising slope=
R
SENSE
*(
V
IN
−V
OUT
)/
L
OUT
The falling slope of this triangular voltage slope can be expressed as follows:
falling slope=−
R
SENSE
*(
V
OUT
/L
OUT
).
This triangular current signal is summed with an internal ramp signal (for duty cycles >50%) and compared with an output voltage error signal to determine the HI and LO signal modulation. As those of ordinary skill in the art will recognize, this closed loop control scheme for output voltage regulation is known as peak current-mode control.
FIG. 2
is a timing diagram illustrating some of switching waveforms for the circuit of FIG.
1
. The D (“drive”) waveform alternates between an ON time (e.g., the time between time points
210
-A and
212
-A in
FIG. 2
) and an OFF time (e.g., the time between time points
210
-A and
212
-A in FIG.
2
). The time between the rising edge of the ON time (e.g., at time point
210
-A shown in
FIG. 2
) and time rising edge of the next ON time (e.g., at time point
210
-B shown in
FIG. 2
) is defined as a “phase” (or “switching cycle”) in the context of the present invention. In a fixed frequency converter, the phase time is determined by an oscillator or other clock source, and the duty cycle is varied to regulate the output voltage, V
OUT
. On the other hand, in a variable frequency converter, the phase time is varied and the ON time typically remains constant to regulate the output voltage, V
OUT
.
Still referring to
FIG. 2
, the voltage across the phase node, SW, essentially follows the waveform of the drive signal D, and alternates in value between V
IN
(during the ON time) and ground (during the OFF time). The HI waveform (which controls the M
UPPER
transistor switch) is essentially 180 degrees out of phase with the LO waveform (which controls the M
LOWER
transistor switch). As shown in
FIG. 2
(with exaggeration, for the sake of explanation) the HI waveform is typically turned OFF slightly before the LO waveform is turned ON to prevent a short circuit or cross conduction condition. Similarly, the LO waveform is typically turned OFF slightly before the HI waveform is turned ON. V
L
is the voltage across the primary winding of inductor L
OUT
. V
L
switches between (V
IN
−V
OUT
) (when the HI waveform is ON) and (−V
OUT
) (when the HI waveform is OFF), essentially following the HI signal. V
OUT
is filtered by output capacitor C
OUT
producing a DC output equal to D*V
in
with a small ripple voltage that follows the polarity of the V
L
voltage. None of the waveforms are drawn to scale in
FIG. 2
, and their values/excursions have been exaggerated in some cases for the sake of clearer explanation.
Various alternative implementations for the switch block
120
of
FIG. 1
are known to those of ordinary skill in the art, some of which are illustrated in FIG.
3
. Referring to
FIG. 3
, the M
LOWER
transistor switch may also be implemented as a diode D
1
as shown in diagram
120
-A, or as a transistor connected as a diode in diagrams
120
-B and
120
-C. Moreover, many other DC-DC converter configurations using current-mode control are known to those of ordinary skill in the art (e.g., boost converters, Cuk converters, step-up configurations, multiple output configurations, fixed frequency converters, variable frequency converters, etc.). As will be described in more detail later in this document, all of these various configurations may implement the virtual current sensing technique according to aspects of the present invention.
Several disadvantages are associated with the method of inductor current sensing described above with reference to
FIGS. 1 and 2
. First, the DC value of the voltage across the current sensing resistor R
SENSE
introduces an output voltage regulation error proportional to DC output current. Second, the signal-to-noise ratio (“SNR”) of the AC portion (or slope amplitude) of the voltage across the current sensing resistor R
SENSE
is low due to switching noise induced from parasitic noise elements in the system. This noise causes inaccuracies in the measured inductor current slope that could result in converter instability and possibly failure. Also, power (having value P=[I
L
2
*R
SENSE
]) is dissipated through the R
SENSE
resistor, and this reduces the overall converter efficiency.
Another method known to those of ordinary skill in the art for sensing inductor current is to measure the voltage drop across the M
UPPER
or M
LOWER
MOSFET (metal oxide semiconductor field-effect transistor) switches when either one is turned ON. This voltage, V
DS
, is equal to the inductor current during the transistor's on-time, I
DS
, multiplied by the on-resistance, R
DS(ON)
, of the transistor. Since different types of MOSFETs have different R
DS(ON)
values, a reference must be programmed into the controller to interpret the relationship between V
DS
and I
DS
. This technique exhibits the following disadvantages in terms o
Andruzzi Joseph M.
Fogg John
Rader, III William E.
Riley Shawn
Ritchie David B.
Semtech Corporation
Thelen Reid & Priest LLP
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