Patent
1996-10-07
2000-02-08
Teska, Kevin J.
39550004, G06F 1750
Patent
active
060235675
ABSTRACT:
An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.
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Osler Peter James
Wilder Tad Jeffrey
Winn Charles Barry
Do Thuan
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Teska Kevin J.
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