Method and apparatus for verifying test information on a backpla

Details Method and apparatus for verifying test information on a backpla Method and apparatus for verifying test information on a backpla

1995-10-17

1997-08-19

Nguyen, Hoa T.

Excavating

3241581, G01R 3128

Patent

active

056595522

ABSTRACT:
Verification of test information transmitted across an 1149.1 backplane test bus between a circuit board (12.sub.1) and a test master (14) is accomplished by having both the test master and the circuit board compute a cheek code for each block of information that is transmitted by, or received at, the board. During intervals other than one of the active Boundary-Scan states, the test master (14) acquires the check codes produced at the circuit board (12.sub.1) and compares them to the corresponding codes generated by the tests master. Any difference between the corresponding codes generated by the test master and the circuit board signifies a transmission error.

REFERENCES:
patent: 4694453 (1987-09-01), Kobayashi et al.
patent: 4729124 (1988-03-01), Hansel et al.
patent: 5068854 (1991-11-01), Chandran et al.
patent: 5132635 (1992-07-01), Kenedy
IEEE Std. 1149.1-1990, "IEEE Standard Test Access Port and Boundary-Scan Architecture," Chapter 5, pp. 5-1-5-17.

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