Boots – shoes – and leggings
Patent
1996-02-13
1998-11-24
Teska, Kevin J.
Boots, shoes, and leggings
364489, G06F 1750
Patent
active
058416722
ABSTRACT:
The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.
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Bures Clementina
Grossman Michael
Misheloff Michael
Salet Marie C.
Schaefer Thomas
Garbowski Leigh Marie
Teska Kevin J.
VLSI Technology Inc.
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