Boots – shoes – and leggings
Patent
1995-12-13
1997-07-22
Trans, Vincent N.
Boots, shoes, and leggings
364489, 364490, 364578, G06F 1750
Patent
active
056509383
ABSTRACT:
A method and apparatus for verifying an integrated circuit design composed of both synchronous and asynchronous regions. The computer implemented system imports a design combining synchronous and asynchronous regions and utilizes a static timing analyzer to automatically determine the boundaries of the asynchronous regions including input and output probe points at the inputs and outputs of the asynchronous regions. The static timing analyzer also generates a netlist of the asynchronous regions as well as certain information indicative of the signal arrival times of data sensed over the input probe points of the asynchronous regions. A functional simulator then uses test vectors generated for the primary inputs of the integrated circuit design and automatically determines a set of test vectors specifically for the asynchronous portion by monitoring the input probe points. This can be done for each asynchronous region. The functional simulator also automatically determines a set of expected output data from the generated test vectors by monitoring the output probe points. A full timing gate-level simulator then processes only the asynchronous regions using the generated test vectors, the asynchronous netlist, and the generated arrival times as input and generates an output which is verified against the expected output.
REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 5191541 (1993-03-01), Landman et al.
patent: 5282146 (1994-01-01), Aihara et al.
patent: 5541849 (1996-07-01), Rostoker et al.
Bootehsaz Ahsan
Levia Oz
Malloy Franklin J.
Pedron Pierrick
Siek Vuthe
Synopsys Inc.
Trans Vincent N.
LandOfFree
Method and apparatus for verifying asynchronous circuits using s does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for verifying asynchronous circuits using s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for verifying asynchronous circuits using s will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1564097