Method and apparatus for verifying a site-dependent wafer

Details Method and apparatus for verifying a site-dependent wafer Method and apparatus for verifying a site-dependent wafer

2008-04-09

2010-06-01

Patel, Ramesh B (Department: 2121)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S110000, C438S011000, C716S030000, C716S030000

Reexamination Certificate

active

07729795

ABSTRACT:
The present invention includes a method of verifying a Site-Dependent (S-D) wafer that includes receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing subsystems, creating a first set of unverified S-D wafers by performing a first S-D creation procedure, establishing S-D wafer state data for each unverified S-D wafer, establishing a first set of evaluation wafers comprising a first number of the unverified S-D wafers, establishing first operational states for a plurality of S-D evaluation elements, determining a first number of available evaluation elements, establishing a first S-D transfer sequence, transferring the first set of S-D evaluation wafers to the first number of available evaluation elements in one or more evaluation subsystems and applying a first corrective action when the number of S-D evaluation wafers is greater than the first number of available evaluation elements.

REFERENCES:
patent: 6885955 (2005-04-01), Atchison
patent: 7087527 (2006-08-01), Hofmann
patent: 7207017 (2007-04-01), Tabery et al.
patent: 7305645 (2007-12-01), Capodieci et al.
patent: 7531368 (2009-05-01), Winkler et al.
patent: 2003/0229410 (2003-12-01), Smith et al.
patent: 2005/0132306 (2005-06-01), Smith et al.
patent: 2006/0074611 (2006-04-01), Wong et al.

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