Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-09-05
2006-09-05
Mai, Tan V. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C716S030000
Reexamination Certificate
active
07103620
ABSTRACT:
A method and an apparatus for verification of arithmetic digital circuits is disclosed, wherein a first circuit, called a specification, is compared for equivalence with a further circuit called an implementation, with equivalence occurring when and only when the specification and implementation always produce the same output signals for the same input signals. The gate level description of the specification and implementation are converted to a network of elementary arithmetic 1-bit operations (XOR, half-adders, full adders) and the equivalence of the specification and implementation is identified in that a comparison of the resultant networks from elementary arithmetic 1-bit operations is carried out directly.
REFERENCES:
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patent: 6851102 (2005-02-01), Tsuchiya
patent: 2003/0121009 (2003-06-01), Bae
R. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE, 1986, pp. 677-691.
D. Brand, “Verification of Large Synthesized Designs,” IEEE, 1993, pp. 534-537.
A. Kuehlmann, “Equivalence Checking Using Cuts and Heaps,” DAC, 1997, pp. 263-268.
Kunz Wolfgang
Rudolf Thomas
Stoffel Dominik
24IP Law Group USA
DeWitt Timothy R.
Mai Tan V.
OneSpin Solutions GmbH
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