Method and apparatus for vector register with scalar values

Details Method and apparatus for vector register with scalar values Method and apparatus for vector register with scalar values

1999-10-20

2003-03-04

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

C712S004000, C712S005000, C712S025000, C708S236000, C708S626000

Reexamination Certificate

active

06530011

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of digital processing architecture. More specifically, the present invention relates to the area of data mixed scalar and vector operations.
2. Description of the Related Art
In typical digital processing systems, processors are designed to be able to operate various data structures to satisfy various requirements, such as speech recognition, imaging processing, and sound emulation. Traditionally, a general data structure is designed to handle general values while a special data structure is often dedicated to handle special cases. For example, a vector data structure is typically a special data structure for handling vectors. Also, a scalar data structure is normally used as a data structure. Typically a scalar value is used for representing a quantitative value which has a single numerical component while a vector value includes multiple numerical components.
A scalar value, such as an area, length, mass, and temperature, is completely described when the magnitude of the quantity is identified. On the other hand, a vector value is not completely described until all related values, such as magnitude and direction, are specified. For example, a vector may describe an automobile's speed as well as its direction. Another example is that a vector may describe a speed, altitude, and direction of an airplane. Traditionally, a typical vector notation is
u=
(
u
1
, u
2
, . . . u
n
)
v=
(
v
1
, v
2
, . . . v
n
)
where u
1
and v
1
are two vector values. The sum u+v is defined by
u+v=[u
1
+v
1
, u
2
+v
2
, . . . u
n
+v
n
)
Since a vector contains more than one value or element, a typical vector data structure, which stores more than one value, can improve system performance in the area of data access and data computations. For example, a vector register may store (u
1
, u
2
) or three values (u
1
, u
2
, u
3
) vector values. Since vector values are stored differently from scalar values, or number of specialized vector execution units are typically employed for handling vector operations.
Consequently, a digital processing system containing vector execution units can typically implement following operations.
A
2
=A
1
op A
0
B
2
=B
1
op B
0
where A and B are vector values. The digital processing system should also be capable of implementing scalar operations. Such as
S
2
=S
1
op S
0
where S is a scalar value.
Although vector data and scalar data are structured differently, many computations require sharing between vector and scalar values. Accordingly, it is desirable to have a system that can implement mixed vector and scalar values in an operation.
SUMMARY OF THE INVENTION
A method and an apparatus of implementing mixed scalar and vector values in a digital processing system is disclosed. In one embodiment, a digital processing system, which contains a processing unit and memories, is capable of identifying a first data in a first scalar register and a second data in a vector register. Upon fetching the first data as a first operand and the second data as a second operand, the processing unit performs an operation between the first and second operands in response to an operator. Upon completion of the operation, the result is subsequently stored in a second scalar register.
In another embodiment, a digital processing device includes a microprocessor and a memory where the memory contains mixed scalar/vector instructions. Each mixed scalar/vector instruction indicates whether the operands are scalar or/and vector values and how to operate mixed scalar/vector operations.


REFERENCES:
patent: 4803620 (1989-02-01), Inagami et al.
patent: 4837730 (1989-06-01), Cook et al.
patent: 5537606 (1996-07-01), Byrne
patent: 5983230 (1999-11-01), Gilbert et al.

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