Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-09-26
2009-10-13
Nguyen, Tuan T (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185260, C365S189040
Reexamination Certificate
active
07602645
ABSTRACT:
There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (e.g., restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (e.g., a microprocessor) or a portion of a memory device (e.g., a discrete memory).
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Daghighian Hamid
de Champs Paul
Popoff Gregory Allan
Innovative Silicon ISi SA
Nguyen Hien N
Nguyen Tuan T
Steinberg Neil A.
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