Method and apparatus for validating I/O addresses in a fault-tol

Details Method and apparatus for validating I/O addresses in a fault-tol Method and apparatus for validating I/O addresses in a fault-tol

1994-12-15

1996-12-17

Beausoliel, Jr., Robert W.

39542111, 395411, 395413, G06F 1100

Patent

active

055862535

ABSTRACT:
A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.

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