Pulse or digital communications – Multilevel – Synchronized
Reexamination Certificate
1996-06-28
2001-11-13
Luther, William (Department: 2664)
Pulse or digital communications
Multilevel
Synchronized
C375S364000
Reexamination Certificate
active
06317469
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the communication of self-clocked multi-level data providing a self-clock utilizing a data processing system; and, more particularly, describes a method and apparatus for associating each of a plurality of digital bits in a series of digital bits with an output level, wherein one output level is associated with a clock output level, and transmitting the output levels utilizing the data processing system. Still more particularly, the present invention relates to generating a series of digital bits and a clock signal in response to receipt of transmitted output levels, each output level being associated with one of a plurality of digital bits or a clock output level.
2. Description of the Related Art
As computer processing speeds have increased, new input/output port interfaces have been developed to deliver data at higher transfer rates. The desire for higher transfer rates has also resulted in the modification of previously known interfaces, such as the modification of the Small Computer Systems Interface, known as SCSI, to “Wide SCSI” and “Fast SCSI”. Some known parallel port interfaces are now capable of transfer rates up to 2 Mbytes/sec.
In order to properly transfer data at the higher transfer rates utilizing parallel interfaces, shielding of the interface cable is required to limit electromagnetic interference Shielding increases the cost of manufacturing such a cables and thus increases the cost associated with transferring data utilizing fast parallel interfaces.
Serial interfaces offer a lower cost solution because fewer cables are required. However, serial interfaces capable of supporting higher transfer rates are also more expensive to manufacture due to increased costs associated with necessary semiconductor processes.
Digital data is typically transferred by first converting the digital data into analog data utilizing a digital-to-analog converter (D/A converter). The analog data is then transmitted through an interface, such as a serial interface of a computer, and is then received at an interface of another device, such as a serial interface of a second computer or an I/O device such as a disk drive. There the data is converted from analog back to digital utilizing an analog-to-digital converter (A/D converter).
The digital data is encoded prior to transmission. Several methods are known for encoding digital data. The most common method is a simple one-to-one correspondence between bits and an analog output. For example, a binary bit “0” is represented by a low voltage while a binary bit “1” is represented by a high voltage. The voltage levels are the analog outputs and are received and decoded in order to reproduce the original digital data.
Another common method is called bi-phase coding, or “Manchester” encoding. In this method only two levels are required. Two transitions are required for each bit. Therefore, a transition from a high voltage level to a low voltage level may represent a binary “0” while a transition from a low level to a high level may represent a binary “1”. A voltage transition occurs only when the digital data stream changes from one binary level to another. Therefore, if the data stream includes a stream of binary “1”'s, a transition occurs at the beginning of the stream and then no additional transition occurs. Because there are predictable transitions upon each bit transition, the receiver can be synchronized upon each transition. Therefore, synchronization occurs upon each bit transition.
Another known method of encoding is known as “bi-polar” encoding. Bi-polar encoding uses three levels to represent the encoded data. Each binary “1” is represented alternatively as either a positive or a negative voltage output level, with a binary “0” represented as an output level in between the positive and negative levels. The polarity of the output level representing a binary “1” alternatives between a positive voltage and a negative voltage for each binary “1” in the data stream.
SUMMARY OF THE INVENTION
A method and apparatus utilizing a data processing system are disclosed for multi-level data communication providing self-clocking. A first digital signal is input which includes a series of digital bits. The series of digital bits comprises a plurality of groups of digital bits. One of a plurality of output levels is associated with each group of data bits for each of the plurality of the digital bits included within the first digital signal. A particular output level is associated with a clock output level. An output signal is generated which includes a transmission of the output level for each of the groups of digital bits and includes multiple transmissions of the clock output level, where a clock output level is transmitted after each transmission of an output level for each of the groups of digital bits.
At the receive end, a clock signal is generated in response to a receipt of the multiple transmissions of the clock output level. A second digital signal is generated, in response to a receipt of the output signal, utilizing the received output levels for each of the groups of digital bits and the received transmissions of the clock output level, so that the second digital signal is the equivalent of the first digital signal.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
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LSI Logic Corporation
Luther William
LandOfFree
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