Coded data generation or conversion – Digital code to digital code converters – Adaptive coding
Reexamination Certificate
2000-10-02
2003-05-13
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Adaptive coding
C375S240250
Reexamination Certificate
active
06563437
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to programmable logic devices (PLDs), and more particularly to PLDs that may be configured according to compressed configuration data stored in a memory device.
BACKGROUND OF THE INVENTION
Programmable logic has increasingly become a valued resource for system designers. Programmable logic can allow for a custom logic design to be implemented without the initial cost, delay and complexity of designing and fabricating an application specific integrated circuit (ASIC).
Currently, there are many variations of programmable logic, including simple programmable logic devices (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs) (referred to herein collectively as programmable logic devices (PLDs)). Such devices typically include programmable logic circuits that can operate in conjunction with corresponding memory circuits. The particular function of a logic circuit can be determined according to data stored in a corresponding memory circuit. A memory circuit is typically a nonvolatile memory circuit, such as a programmable read-only-memory (PROM), an electrically programmable ROM (EPROM), and/or electrically erasable and programmable ROM (EEPROM), including “flash” EEPROMs.
As PLDs grow in size and complexity, the amount of configuration data for such PLDs can grow correspondingly. Thus, larger density memory devices may be required to store configuration data. Unfortunately, larger density memory devices may be more expensive and/or more difficult to procure than smaller density memory devices, and thus can increase the overall cost of a system.
In many configurations, in response to a particular event, such as the application of power (boot-up) or a reset condition, a PLD may receive configuration from a corresponding memory device. Such data may be in the form of a serial data stream.
To reduce the amount of memory that may be required to store configuration data and/or to reduce the amount time to transfer configuration data from a memory device to a PLD, configuration data may be “compressed.” Compression may occur according to a predetermined algorithm. As but one example, a Huffman compression algorithm may map particular values to Huffman codes according to the frequency of occurrence for such values. However, conventional compression/decompression approaches may have drawbacks.
Referring now to
FIG. 9
, a conventional PLD programming approach
900
is shown that includes a PLD
902
and an associated read-only-memory (ROM)
904
. A ROM
904
may store configuration data that has been compressed according to a predetermined algorithm. A PLD
902
may include a decompression circuit
906
and programmable logic circuits
908
. A decompression circuit
906
may include fixed circuits designed to execute a predetermined decompression algorithm.
In response to a predetermined condition (e.g., boot-up or reset), a PLD
902
may communicate with a ROM
904
and read configuration data that can establish the function of programmable logic circuits
908
. Because such configuration data may be compressed, decompression circuit
906
may decompress configuration data before the data is programmed into programmable logic circuits
908
.
The use of compressed configuration data and an integrated fixed decompression circuit can reduce the amount of ROM storage that may be required to configure a PLD. However, such an approach may include inherent drawbacks.
One drawback to a conventional approach, such as that shown in
FIG. 9
, can be the additional area on a PLD die that a decompression circuit may consume. That is, a decompression circuit can consume die area that might otherwise be dedicated additional programmable logic circuits. Such increases in die size can translate into increased cost, as fewer dice may be formed on a semiconductor wafer.
Another drawback to conventional approaches, such as that shown in
FIG. 9
, can be lack of flexibility. In particular, for optimum efficiency and/or ease of use, it can be desirable to compress configuration data using any of a variety of approaches/algorithms. However, because a decompression circuit (such as that shown as
906
in
FIG. 9
) can be designed for one particular form of compression, such conventional approaches may only accommodate one type of compression/decompression.
FIG. 10
shows a conventional method of programming a PLD. A conventional method is shown in a block diagram and designated by the general reference character
1000
. A conventional method may first include initiating a configuration operation (step
1002
). Such a step may include establishing that a memory device and PLD are functioning properly, and initiating a communication path between a PLD and a memory device.
A conventional method
1000
car further include reading compressed data
1004
from a memory device (step
1006
). Such a step may include reading data from a predetermined set of addresses. Data may be compressed according to a compression algorithm.
Compressed data may then be decompressed (step
1008
). Such a step may include applying compressed data to circuits that are designed to decompress according to a particular decompression algorithm.
Uncompressed data may then be programmed into a PLD to establish the function of the PLD (step
1010
). If all compressed configuration data has not been read and programmed, a method may repeat steps
1006
to
1010
. If the last of the configuration data has been read and programmed, programming operations can end (steps
1012
).
In light of the above discussion, it would desirable to arrive at some way of decompressing configuration data for a PLD that does not necessarily consume as much die area on a PLD as conventional approaches.
It would also be desirable to arrive at some way of providing a way of decompressing configuration data for a PLD that may accommodate more types of compression than conventional approaches.
SUMMARY OF THE INVENTION
The present invention includes a programmable logic device (PLD) and programming method for a PLD. According to various embodiments, a PLD may provide more efficient use of die area and/or more flexibility when being programmed with compressed configuration data.
According to one aspect of the embodiments, a first portion of a PLD may be programmed to function as a particular decompression circuit. A decompression circuit of a first portion may then decompress compressed configuration data for a second portion of the PLD. If desired, the first portion may then be reprogrammed to perform some other function. In addition, or alternatively, a first portion may be reprogrammed to provide a different decompression function.
According to another aspect of the embodiments, a first portion of a PLD can have a reset configuration that includes a decompression circuit. A decompression circuit of a first portion may then decompress compressed configuration data for a second portion of the PLD. A first portion may then be reprogrammed as noted above.
According to another aspect of the embodiments, a PLD may include a number of selectable fixed decompression circuits integrated on the same die as programmable circuits. One of the fixed decompression circuits can be selected to decompress compressed configuration data for programming the programmable circuits.
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Lacey Timothy M.
Landry Greg J.
Cypress Semiconductor Corporation
Sako Bradley T.
Wamsley Patrick
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