Method and apparatus for using extended-data output memory devic

Details Method and apparatus for using extended-data output memory devic Method and apparatus for using extended-data output memory devic

1996-12-31

2000-03-07

Peikari, B. James

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523001, 365203, 365235, 365222, G11C 800

Patent

active

060349190

ABSTRACT:
A memory system including a memory controller that operates in conformity with fast page mode (FPM) memory devices and an extended-data output (EDO) memory device configured to operate with the FPM memory controller by having an output enable input receiving a column address strobe (CAS) signal from the memory controller. The EDO memory device terminates its data cycle upon negation of the CAS signal, so that it operates in a similar manner as an FPM memory device. This prevents data corruption and bus cycle contention. The memory system includes a memory board coupled through a memory board connector, which receives the CAS signal from the memory controller. The memory board includes one or more module connectors, each having an output enable contact receiving the CAS signal. The EDO memory device is mounted on a memory module and includes an output enable input pin which receives the CAS signal when the memory module is plugged into the memory board. In this manner, a computer including a memory system implemented to operate with FPM memory may be upgraded to EDO memory.

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