Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1997-01-27
2004-03-02
Jones, Hugh (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06701289
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention—The present invention generally relates to the optimization of circuit designs and more particularly relates to a method and apparatus for using a placement tool to manipulate cell substitution lists.
2. Description of the Prior Art—Integrated circuit, printed circuit board and other related technologies are advancing at a very rapid rate. The latest generation of integrated circuits can incorporate over four times the circuitry than was possible just a few years ago. Further, circuit board and multi-chip module technology has allowed much denser circuit board designs. These and other advancements have allowed the development of increasingly complex and high speed computer systems.
The design of such computer systems has become increasingly difficult and time consuming. To maximize performance and minimize the size and power of such computer system, designers often implement much of the hardware in a number of integrated circuits. For maximum performance, the integrated circuits are often custom or semi-custom designed. Each integrated circuit may contain several hundred thousand gates, and each gate must be placed and routed in accordance with an overall computer system specification, all on a die typically measuring less than 625 mils on a side.
The overall system specification typically defines the overall function of the computer system, including the power and timing requirements thereof. Because of the size and complexity of such computer systems, system designers often partition the overall design into a number of blocks, wherein each of the blocks performs a dedicated function. Partitioning is typically continued until the size of each of the sub-blocks is of a manageable size. A specification for each of the sub-blocks is then written to define the function, timing and power requirements thereof. Often, one or more of the sub-blocks are implemented in an integrated circuit.
After the sub-block specifications have been defined, logic designers typically enter a schematic into a design database for each sub-block, using selected components from a component library. The schematic is typically entered via a schematic entry tool running on an engineering workstation, and the design database is typically stored therein.
The component library may include a number of cells wherein each of the cells implements a different function. For example, the component library may include NAND gates, NOR gates, XOR gates, registers, latches, I/O cells, etc. Further, each of the individual cells may have a logically equivalent component with a different drive strength. The desirability of having different drive strength cells within the component library is discussed in more detail below.
In addition to the above, each of the cells typically have a number of “representations” stored in the component library. For example, a cell may have a “symbolic representation”, a “schematic representation”, and a “physical representation”. When entering the schematic, the designer typically provides the “symbolic representation” directly on the schematic sheet via a schematic editor, and interconnects the symbols to achieve the desired function.
After the schematic has been entered into the design database, the schematic may be processed, or expanded, into a design netlist. The design netlist typically identifies each of the library cells that are used in the schematic, and further identifies the interconnections therebetween. The netlist is often written in an EDIF (Electronic Design Interface) format. EDIF is an industry wide standard, developed to allow the design netlist to be compatible with various software programs developed by different vendors.
An alternative approach for entering the design into a design database involves using sophisticated synthesis tools. The word “tool” as used herein refers to a software program running on a data processing system or an application specific data processing system. In such an approach, the designer enters logical equations describing the behavior (i.e. function) of the circuit design. A first synthesis tool implements the logical equations using logical cells from the component library. A second synthesis tool may then minimize the logic using known techniques, and may attempt to optimize the design based on a number of predetermined factors. For example, the designer may direct the synthesis tool to optimize the design for speed, power, or some other factor.
Typically, the resulting design netlist is provided to a place and route tool. There are a number of place and route tools available op the market today. The place and route tool may read the “physical representation” of each cell within the design and place the physical representation within an imaginary two dimensional box. For integrated circuit designs, the imaginary box often corresponds to the physical boundary of the resulting integrated circuit die.
Once all of the cells have been placed, the place and route tool interconnects the cells in accordance with the design netlist. Depending on the technology and the power bussing strategy of the component library, the place and route tool may provide the required interconnections (or routes) using up to five layers of metal.
Initially, the place and route tool may not take into account critical timing paths or other design parameters.
However, most modern place and route tools have the capability of biasing the placement and routing of the cells to favor predetermined nets within the design database.
In some cases, it is advantageous to manually place certain critical cells within the design. The manual placement of these cells is typically accomplished via a placement tool (e.g. floor-planning tool). Stand alone floorplanning tools are available. However, many place and route tools have at least a limited floor-planning or placement capability. After selected critical cells are manually placed by the designer, the remaining cells may be placed and the circuit design may be routed as described above.
The output of the place and route tools is typically a netlist in the EDIF format. In most large designs, the place and route netlist is hierarchical in nature. Thus, the place and route netlist typically only identifies the placement coordinates and orientation of each of the cells within the design, and does not contain the actual physical representation of each cell. Rather, the place and route netlist contains pointers to the physical representations stored in the component library. Thus, if a particular cell is used a number of times within the design, only one copy of the physical representation is required to be stored. The place and route netlist typically also identifies the interconnections, or routes, by the coordinates of the starting, ending, and any other points where the route changes direction. Further, the width of the route is also identified.
After the place and route netlist is generated, the designer may use an extraction tool to extract an RC file therefrom. The extraction tool may process the place and route netlist and may determine the resistance, capacitance, or any other parameters selected by the designer, for each net in the design. For example, the extraction tool may determine the capacitance of a particular net by calculating the input load capacitance for each gate connected to the net, and may further determine the capacitance between a corresponding route and, any other layer within the design, including the substrate. That is, the extraction tool may determine what layers the particular route overlaps, and may calculate the capacitance generated therebetween.
To provide accurate results, the extraction tool is often provided with technology specific parameters including oxide thicknesses between metal layers, the permittivity of each of the oxide layers, etc. These technology specific parameters are often stored in a technology file, which may be read by the extraction tool.
After the extraction tool provides an RC file for the design, the RC file and the origin
Aubel Mark D.
Garnett Robert E.
Kerzman Joseph P.
Rezek James E.
Johnson Charles A.
Jones Hugh
Nawrocki, Rooney & Sivertson P.A.
Starr Mark T.
Unisys Corporation
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