Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2001-02-13
2002-06-11
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S218000
Reexamination Certificate
active
06404260
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to generating a clock signal within a semiconductor chip. More specifically, the present invention relates to a method and an apparatus that uses a non-periodic signal to modulate the period of a clock signal in order to reduce the size of spikes of electromagnetic radiation generated by a circuit that uses the clock signal.
2. Related Art
Most semiconductor chips, including microprocessor chips, make use of an internal clock signal to synchronize various clocked circuit elements. This internal clock signal is typically generated by a clock synthesizer circuit that produces a periodic clock signal, which propagates through a clock distribution network to the various clocked circuit elements.
For example,
FIG. 1
illustrates a clock synthesizer circuit located on a semiconductor chip
100
. This clock synthesizer circuit receives a signal from an external clock
102
, and multiplies the frequency of this signal to produce a clock signal
107
, which is distributed through clock distribution network
110
to various clocked circuit elements within semiconductor chip
100
. This clock synthesis circuit is comprised of a number of sub-circuits, including divider circuit
112
, phase detector circuit
104
, filter
106
and voltage-controlled oscillator (VCO)
108
.
Divider circuit
112
receives feedback signal
105
as an input, and divides the frequency of feedback signal
105
by an integer value to produce an output signal
103
that feeds into phase detector circuit
104
. This integer value specifies a multiplicative relationship between the signal from external clock
102
and output clock signal
107
. For example, if the signal from external clock
102
has a frequency of 400 megaHertz, and divider circuit
112
divides by the integer
5
, the frequency of output clock signal
107
is 5×400 megaHertz=2 gigaHertz. Note that divider circuit
112
may be programmed to use different integer divisor values.
Phase detector circuit
104
compares the output of divider circuit
112
against the signal from external clock
102
and produces a voltage that feeds through filter
106
into VCO
108
. This voltage varies as a function of a difference in phase between signal from external clock
102
and the output of divider circuit
112
.
Filter
106
includes a low pass filter to filter out high frequency components from the output of phase detector circuit
104
.
VCO
108
uses the output of filter
106
to control the frequency of output clock signal
107
. Note that the signal from external clock
102
and feedback signal
105
are used to control the frequency of output clock signal
107
through a classic phase-locked loop arrangement.
This periodic clock signal triggers periodic transitions in the clocked circuit elements. These transitions typically occur on clock edges (see FIG.
2
), and produce electromagnetic (EM) radiation, which is concentrated in spikes located in specific frequencies. For example, in a periodic signal, these spikes are located at the frequency of the clock signal, and at the various harmonics of the clock signal (see FIG.
3
).
As computer designers pack larger amounts of circuitry into a single semiconductor chip, the number of clocked components in the chip increases, and the total electromagnetic radiation generated by the chip (at the clock frequency) increases.
In larger chips, such as newer microprocessors, electromagnetic radiation can produce detrimental interference in nearby electrical components. This problem is becoming progressively worse as the number of components that can be integrated into a semiconductor chip continues to increase at an exponential rate.
In order to remedy this problem, a clock synthesizer has been proposed to change the time interval between successive transitions of the clock signal, by using a second lower-frequency signal to modulate the frequency of the clock signal (see “Dual Loop Spread Spectrum Clock Generator,” by Hung-Sung Li, Yu-Chi Cheng and Deepraj Puar, Digest of Technical Papers of the 1999 IEEE International Solid-State Conference, pp. 184-185.) Under this scheme, the clock signal repeats itself after a large number of clock cycles, instead of a single cycle.
Even though this scheme can reduce the size of the EM spikes, the signal is still periodic in the time domain. Consequently, there still exists clearly defined EM spikes at specific frequencies.
What is needed is a method and an apparatus for generating a clock signal that does not create sharp EM spikes at specific frequencies.
SUMMARY
One embodiment of the present invention provides a system that uses a non-periodic signal to modulate the period of a clock signal. The system includes a latch with a latch input, a latch output and a clock input. Asserting the clock input of the latch causes a data value at the latch input to be stored into the latch, and to thereby appear at the latch output. The system also includes an inverting delay circuit that receives the clock signal from the latch output and generates an inverted and delayed clock signal, which feeds back into the input of the latch. The clock input of the latch is coupled to the non-periodic signal, so that the non-periodic signal is used to latch the inverted and delayed clock signal, so that the clock signal changes at a non-periodic interval.
In one embodiment of the present invention, the inverting delay circuit includes a chain of an odd number of inverters.
One embodiment of the present invention additionally includes a chaotic circuit containing three or more energy storage elements for generating the non-periodic signal. In a variation on this embodiment, the chaotic circuit is made up of a number of components, including: a first resistor with a first end and a second end, a first capacitor coupled between ground and the first end of the first resistor, a first inductor coupled in parallel with a first capacitor, a non-linear resistor coupled between the second end of the first resistor and ground, and a second capacitor coupled in parallel with the non-linear resistor. Note that in one embodiment of the present invention, the first capacitor is a variable capacitor, and the second capacitor is a variable capacitor.
In a variation on this embodiment, an output of the chaotic circuit feeds through a comparator to ensure that the non-periodic clock signal moves from rail to rail.
In a variation on this embodiment, the chaotic circuit includes an adjustment mechanism that can be used to adjust the average period of the non-periodic signal in order to adjust a variance in the period of the clock signal.
In one embodiment of the present invention, the inverting delay circuit includes an adjustment mechanism that can be used to adjust a delay through the inverting delay circuit.
In one embodiment of the present invention, the inverting delay circuit includes a chain of an odd number of inverters, and the adjustment mechanism for the inverting delay circuit includes a variable capacitor coupled between an output of an inverter and ground.
In one embodiment of the present invention, the inverting delay circuit includes a chain of an odd number of inverters, and the adjustment mechanism for the inverting delay circuit includes, a first variable resistor coupled between a voltage source and a drain of a P-type transistor of a first inverter, and a second variable resistor coupled between ground and a drain of a N-type transistor of the first inverter.
One embodiment of the present invention additionally includes a clock distribution network for distributing the clock signal to circuit elements on a semiconductor chip.
REFERENCES:
patent: 4270220 (1981-05-01), Hagiwara et al.
patent: 5231319 (1993-07-01), Crafts et al.
patent: 5727038 (1998-03-01), May et al.
patent: 5923676 (1999-07-01), Sunter et al.
patent: 6259754 (2001-07-01), Jeong
Publication entitled “Dual-Loop Spread-Spectrum Clock Generator,” by Hung-Sung Li, et al., International Solid-State Circuits Conference, , Session 10, Paper TA 10.5, Feb.
Cox Cassandra
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
Wells Kenneth B.
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