Patent
1997-07-14
1998-06-02
Shah, Alpesh M.
395733, 39580001, G06F 1300
Patent
active
057614270
ABSTRACT:
In an asynchronous transfer network (ATM), to prevent the bottleneck associated with a host central processing unit (CPU) trying to receive status information for a plurality of interrupts occurring over an interface input/output (I/O) bus, a method and apparatus which transfers all status information directly to the host memory without host involvement. The host CPU is then notified of this new status information via an interrupt. When status information is transferred to the host memory, consistency is ensured and the number of spurious interrupts are reduced. A host software driver may then read the latest status information from the interface I/O bus at its convenience any not incur any performance penalties of I/O accesses.
REFERENCES:
patent: 4777595 (1988-10-01), Strecker et al.
patent: 4972368 (1990-11-01), O'Brien et al.
patent: 4999768 (1991-03-01), Hirokawa
patent: 5067123 (1991-11-01), Hyodo et al.
patent: 5193149 (1993-03-01), Awiszio et al.
patent: 5446726 (1995-08-01), Rostoker et al.
patent: 5506847 (1996-04-01), Shobatake
patent: 5535197 (1996-07-01), Cotton
Ben-Nun Michael
Ramakrishnan Kadangode K.
Roman Peter J.
Shah Bhupendra
Digital Equipment Corporation
Johnston A. Sidney
Kozik Kenneth F.
Shah Alpesh M.
LandOfFree
Method and apparatus for updating host memory in an adapter to m does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for updating host memory in an adapter to m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for updating host memory in an adapter to m will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1471533