Patent
1995-05-30
1997-01-14
Treat, William M.
39518314, 39518306, 39518307, 395568, G06F 1125, G06F 1134
Patent
active
055948642
ABSTRACT:
Methods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An instruction queue and an instruction control unit within a pipelined central processor unit (CPU) provide for grouping and issuing multiple instructions per clock cycle for overlapped execution. Additionally, instruction and data caches in operation with integer and floating point function units issue a program counter to the instruction cache, which subsequently supplies instructions to integer and floating point instruction queues. Both integer and floating point unit datapaths comprise fetch, decode, execute, and writeback stages. In the preferred embodiment, ten additional datalines transmitting PIPE signals are routed from the integer and floating point function units to contact pins on an external pin gate array supporting the CPU. The ten PIPE signals provide information on activity of key internal states of the pipelined processor within a single clock cycle. The PIPE signals may be monitored by a logic analyzer, thereby forming an external hardware monitor. By tracing the ten PIPE signals, the number of instructions issued in each stall-free cycle and total number of cycles elapsed may be determined, permitting determination of bottlenecks in customer software on the target CPU, as well as yielding information for optimizing the CPU to execute customer software more efficiently. Based on the accumulated and tabulated performance data, a CPU vendor can reconfigure hardware and/or software to more precisely meet customer workload needs based on determination of customer software operating in the customers actual work environment.
REFERENCES:
patent: 4879646 (1989-11-01), Iwasaki et al.
patent: 5321828 (1994-06-01), Phillips et al.
William M. Johnson, Superscalar Microprocessor Design, Prentice-Hall, 1991, pp. 32-37 and 63-65.
Lee et al., "Branch Prediction Strategies and Branch Target Buffer Design," Computer, Jan. 1984, pp. 6-22.
"Motorola's 68332 Eliminates Glue Logic," Microprocessor Report, Jun. 1989, p. 10(3).
Stephen Magnus, "Payoff for IC, Analyzer Cooperation; Better Logic Analyzer Interfaces Are Showing Up Sooner for More Complex (Microprocessors)", EDN, Jun. 14, 1990, p. 1(4).
Sun Microsystems Inc.
Treat William M.
LandOfFree
Method and apparatus for unobtrusively monitoring processor stat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for unobtrusively monitoring processor stat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for unobtrusively monitoring processor stat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1395347