Method and apparatus for uniform and efficient handling of multi

Details Method and apparatus for uniform and efficient handling of multi Method and apparatus for uniform and efficient handling of multi

1996-05-07

1998-06-02

Lall, Parshotam S.

395733, G06F 946

Patent

active

057614920

ABSTRACT:
An integrated circuit having a digital processor, a decode stage for decoding an instruction from the instruction set, an execute stage coupled to the decode stage for executing the instruction, and event logic coupled to the decode stage operable to provide an event commands to the decode stage to override the instruction. In one embodiment, an integrated circuit having a pipelined processor handles multiple precise events through the decode stage and execute stage through a process which includes the steps of detecting a plurality of events and issuing an event command, selecting a highest priority event from said the of events, providing an event vector and a link address for the highest priority event, and allowing the event vector and the link to be modified for a higher priority event until the event command is issued to the execute stage.

REFERENCES:
patent: 4779195 (1988-10-01), James
patent: 5193158 (1993-03-01), Kinney et al.
patent: 5537559 (1996-07-01), Kane
patent: 5568643 (1996-10-01), Tanaka
patent: 5579498 (1996-11-01), Ooi

Affiliated with

Also associated with

Rating

Method and apparatus for uniform and efficient handling of multi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for uniform and efficient handling of multi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for uniform and efficient handling of multi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1472453