Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-02-21
2004-06-01
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000, C327S427000, C323S315000, C323S316000
Reexamination Certificate
active
06744303
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to MOS circuits and, more particularly, to compensation for tunneling leakage current in MOS circuits.
BACKGROUND OF THE INVENTION
It is common practice to use the existing gate oxide, or dielectric between the gate and bulk node of a MOS device, typically a PMOS or NMOS device, as a dielectric for making the MOS device into a capacitor. A typical configuration for making a PMOS device into a capacitor is to connect the source and the drain, also collectively called diffusions in this configuration, and the N-well tie to a first supply voltage, typically Vdd. The gate is then connected to the desired node, which is typically coupled to other devices. Typically, the desired node has a more negative potential on it than the potential on the source and the drain, i.e., the diffusions.
In this capacitor configuration of a PMOS device, there could be a DC current flowing from the source and drain, i.e., the diffusions, through the oxide into the gate terminal, particularly if the oxide is very thin. This DC current flowing from the source and the drain to the gate is a parasitic current known to those of skill in the art as “gate capacitor leakage current” or simply “gate current”. Herein, gate capacitor leakage current, or gate current, is also referred to as “tunneling leakage current”.
In the prior art, i.e., in 0.25 micron or greater processes, the thickness of the gate oxide layer making up the gate was large enough that the tunneling leakage current was minimal and considered negligible and, therefore, was often ignored. However, to accommodate smaller feature sizes, faster clock speeds, advances in low power circuits, 0.18, 0.15, 0.13 micron processes are becoming the standard, and the thickness of gate oxide layers has been steadily decreasing. Indeed, at the time of this application gate oxide layer thickness is approaching 20 angstroms and will soon be even thinner. Consequently, the ability of the gate oxide layer to insulate, and thereby keep the tunneling leakage current minimal, is constantly decreasing. As a result, in deep submicron semiconductor processes, tunneling leakage current is no longer considered negligible and is seen as a serious problem.
Unfortunately, tunneling leakage current may vary as an exponential function of the voltage between the gate and the source (Vgs) of the MOS device. In addition, when the MOS device is configured as a capacitor, i.e., the gate is used as a capacitor, it is particularly difficult to compensate for tunneling leakage current since the gate often needs to remain a “floating node” and, therefore, cannot be driven by any external voltage source to create a corrective biasing Vgs.
Some prior art “solutions” have been attempted to “solve” the problem of tunneling leakage current, however, these solutions: tended to significantly change the characteristics of the capacitor, and therefore affect the efficiency and operational parameters; were often based on the use of non-standard, ultra precise custom components; and/or required a prohibitively large number of additional components.
For instance, prior art “work around” solutions included reducing the operational range of the capacitor or changing the diffusion and well voltage potentials to match the gate potential. Another prior art “solution” to the tunneling leakage current problem was to use two identical capacitors, each having one-half the capacitance of the active capacitor. According to this prior art “solution”, one capacitor's diffusions were configured like the active capacitor and the other capacitor was connected to the floating node while the gate oxide layer was connected to the second supply voltage, Vss. The thought behind this prior art “solution” was to drain off a current equal to the gate leakage current. However, two capacitors rarely have identical characteristics and this prior art “solution” required two capacitors. In addition, the resulting circuit was more susceptible to power supply noise.
As discussed above, the prior art “solutions” shown above tended to significantly change the characteristics of the capacitor, and therefore affect the efficiency and operational parameters of the filter, were based on the use of non-standard, ultra precise custom components, and/or required a significant number of additional components. Consequently, the prior art “solutions” were, at best, flawed work arounds that failed to effectively address the problem of tunneling leakage current discussed above. Therefore, in the prior art, either: the gate oxide layer thickness was increased, a very costly and undesirable option; tunneling leakage current was simply assumed and designed around; or the use of MOS devices as filter capacitors was abandoned completely.
Tunneling leakage current is particularly problematic when the MOS device, configured as a capacitor as discussed above, is used as a filter capacitor in a PLL. In these instances, tunneling leakage current leads to a significant static phase error that causes setup time violations and, worse, can potentially cause loss of the lock. This is especially true if the phase-frequency detector runs at a slow speed.
What is needed is a method and apparatus for compensating for tunneling leakage current that does not significantly change the characteristics of the capacitor, uses standard components and requires a minimal number of additional components.
SUMMARY OF THE INVENTION
The present invention is directed to a method and apparatus for compensating for tunneling leakage current through a capacitor. According to the invention, a first capacitor, in one embodiment of the invention a MOS device configured as a capacitor, has a parasitic DC tunneling leakage current “Ig”. According to the present invention, tunneling leakage current Ig is compensated for by a compensation circuit.
In one embodiment of the invention, the compensation circuit includes: an operational amplifier, connected in a negative feedback configuration; a first compensation transistor; a second compensation transistor; and a compensation capacitor, in one embodiment of the invention a MOS device configured as a compensation capacitor.
According to the invention, the compensation capacitor is chosen so that the ratio of the area of the compensation capacitor divided by the area of the first capacitor is a predetermined area ratio “AR”. The operational amplifier (opamp), in negative feedback, sets the gate voltage of the compensation capacitor to be the same as the gate voltage of the first capacitor.
According to the invention, the first compensation transistor and the second compensation transistor are chosen so that the ratio of the size of the second compensation transistor divided by the size of the first compensation transistor is also the area ratio “AR”. Consequently, since the opamp sets the gate voltage of the compensation capacitor to be the same as the gate voltage of the first capacitor, the first compensation transistor and the second compensation transistor then drain current out of the compensation capacitor and first capacitor, respectively, approximately equal to the amount tunneling leakage current through the compensation capacitor and first capacitor, respectively. Therefore, the potentially adverse effects of the tunneling leakage current Ig through the first capacitor are neutralized by the current drained off through second compensation transistor.
Using the method and apparatus of the present invention, tunneling leakage current is compensated for without changing the characteristics of the capacitor and by using standard components. In addition, the method and apparatus of the present invention requires a minimal number of additional components.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.
REFERENCES:
patent: 6255897 (2001-07-01), Klemmer
patent: 6617835 (2003-09-01), Nishimura
patent: 6683489 (2004-01-01), Eker
Gunnison McKay & Hodgson, L.L.P.
McKay Phillip J.
Nguyen Long
Sun Microsystems Inc.
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