Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-08-13
2003-12-16
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S133000, C341S136000, C341S121000
Reexamination Certificate
active
06664909
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to the field of digital-to-analog conversion. More particularly, the present invention is directed to a method and apparatus for trimming a digital-to-analog converter (DAC) with nonvolatile trimmable current sources to provide a high-resolution current-steering-type DAC.
BACKGROUND OF THE INVENTION
Digital-to-analog converters are well known in the art. These devices take a digital input word and output an analog value corresponding to the magnitude of the digital input word. The current-steering-type of DAC provides its analog output as a current value. Thus, as typically configured, a small magnitude digital input word results in a small output current and a large magnitude digital input word results in a correspondingly large output current. Current steering DACs are useful in a plethora of applications, particularly any type of application where digital control is used and an analog output is required. For example, emerging standards for communications systems require DACs with sample rates in the hundreds of millions of samples per second and resolutions of 10-14 bits or more. The sample rate is simply the number of times per unit time period that the DAC looks at a new input and generates a new output. The resolution refers to the size in bits of the digital input word. A one-bit resolution would correspond to only two possible output states. A 14-bit resolution corresponds to 2
14
(16384) output states. Additional constraints are imposed by the desire to fabricate such devices in conventional CMOS (complementary metal oxide semiconductor) processes without the need for additional masks, process steps, components or materials. At its most basic level, a “standard CMOS” process only requires that the process provide nMOS (n-channel MOSFETs) and pMOS (p-channel MOSFETs) transistors and conductive interconnect between and among them.
Some of the goals in fabricating such devices include low power dissipation, small die area, and compatibility with standard CMOS processing so that both digital and analog circuitry can exist on the same chip without modifying the fabrication process. Since it is desirable to be able to integrate such devices as part of system on a chip (SOC) integrated products, the latter goal is particularly important.
Current steering DACs are attractive for these applications because they are fast and can drive an output load without a voltage buffer. Their linearity, however, is limited by mismatch in the current-source transistors. This means that individual current-source transistors are difficult to fabricate so that they provide identical or perfectly scaled performance. Inherent imprecision in the fabrication process means that the performance of two near-identical transistors will only be able to be somewhat similar. To reduce the impact of this mismatch phenomenon, some mechanism is needed to match or average the performance of the current-source transistors so that they behave nearly ideally. In the past, designers have used several different mechanisms to achieve these goals. For example, laser-trimmable components, such as cermet or nichirome resistors, have been used to attempt to match the performance of transistors to an ideal. Large transistors have also been used to try to minimize mismatch. These approaches are undesirable because they increase the die area used by the DAC. Moreover, trimmable resistor components are undesirable because they take relatively large amounts of die area and require special processing steps not compatible with SOC integration. Randomized layouts have also been used as have architectures where plural transistors are used for each current steering element in order to average out performance differences among nearly identical transistors. Such intrinsic matching approaches generally require complicated layout techniques that usually result in a substantial adverse impact on die size and chip yield. Electrical trimming with on-chip capacitors has been used but requires continuous calibration of the current sources in the DAC because the calibration information held in the capacitors is continuously degrading due to leakage currents. Continuous calibration approaches are undesirable in general because they suffer from the effects of switching noise and require complicated circuitry to adjust current sources on the fly without impacting the performance of the DAC. Accordingly, it would be desirable to have an approach to transistor matching that combines the flexibility of electrical trimming with the dynamic stability of intrinsic matching.
BRIEF DESCRIPTION OF THE INVENTION
A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.
REFERENCES:
patent: 4864215 (1989-09-01), Schouwenaars et al.
patent: 5243347 (1993-09-01), Jackson et al.
patent: 5332997 (1994-07-01), Dingwall et al.
patent: 5376935 (1994-12-01), Seligson
patent: 5666118 (1997-09-01), Gersbach
patent: 5790060 (1998-08-01), Tesch
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5825317 (1998-10-01), Anderson et al.
patent: 5841384 (1998-11-01), Herman et al.
patent: 5870044 (1999-02-01), Dell'ova et al.
patent: 5952946 (1999-09-01), Kramer et al.
patent: 5955980 (1999-09-01), Hanna
patent: 6118398 (2000-09-01), Fisher et al.
patent: 6130632 (2000-10-01), Opris
patent: 6169503 (2001-01-01), Wong
patent: 6191715 (2001-02-01), Fowers
patent: 6317066 (2001-11-01), Chiang
patent: 2002/0089440 (2002-07-01), Kranz et al.
Vittoz, “Dynamic Analog Techniques”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 4, 1994, pp. 97-124.
Vittoz, “Continuous-Time Filters”, Design of Analog-Digital VLSI Circutis for Telecommunications and Signal Processing, Chapter 6, 1994, pp. 177-211.
Vittoz, “Analog-Digital Conversion Techniques for Telecommunications Applications”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 9, 1994, pp. 289-315.
Vittoz, “Delta-Sigma Data Converters”, Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, Chapter 10, 1994, pp. 317-339.
Jose Bastos et al., entitled, “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC”, Dec. 1998, IEEE Journal of Solid-State Circuits, vol. 33, No. 12, pp. 1959-1969.
Geert A. M. Van der Plas et al., entitled, “A 14-bit Intrinsic Accuracy Q2Random WalkCMOS DAC”, Dec. 1999, IEEE Journal of Solid-State Circuits, vol. 34, No. 12, pp. 1708-1718.
Alex R. Bugeja et al., entitled, “A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance”, Dec. 1999, IEEE Journal of Solid-State Circuits, vol. 34, No. 12, pp. 1719-1732.
Alex R. Bugeja et al., entitled, “A Self-Trimming 14-b 100-MS/s CMOS DAC”, Dec. 2000, IEEE Journal of Solid-State Circuits, vol. 35, No. 12, pp. 1841-1852.
Diorio Christopher J.
Figueroa Miguel E.
Hass Terry D.
Humes Todd E.
Hyde John D.
Impinj, Inc.
Nguyen Khai
Ritchie David B.
Thelen Reid & Priest LLP
Tokar Michael
LandOfFree
Method and apparatus for trimming high-resolution... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for trimming high-resolution..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for trimming high-resolution... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3161411