Method and apparatus for transporting messages between processor

Details Method and apparatus for transporting messages between processor Method and apparatus for transporting messages between processor

1995-06-15

1999-07-20

An, Meng-Ai T.

Electrical computers and digital processing systems: multicomput

Computer conferencing

709200, G06F 1300

Patent

active

059250992

ABSTRACT:
A message unit that provides a hardware queue interface between a host processor and a local processor handling I/O operations in an I/O platform. Circuitry manages the head and tail pointers of an inbound free queue, an inbound post queue, an outbound free queue and an outbound post queue. Circuitry is also provided for enabling a host processor or bus agent to access these queues in a single bus transaction by reading or writing inbound port registers or outbound port registers. The queue elements contain handles of message buffers. The invention automatically performs the specific task of locating the next element in a queue, altering that element, and modifying a queue descriptor (i.e., a head or a tail pointer) to indicate the next element for a next queue access. A plurality of registers are used for selectively interrupting either the host processor or the local processor when the queues are written to by either the host processor, a bus agent, or the local processor.

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Ramachandran et al., "Hardware Support for Interprocess Communication", IEEE Transactions on Parallel and Distributed Systems, Jul. 1990, pp. 318-329.

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