Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-03-15
2003-02-25
Ton, Dang (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395100, C370S465000
Reexamination Certificate
active
06526053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packet transmitting apparatus which can be applied to, for example, various nodes such as an ATM (Asynchronous Transfer Mode) switchboard and the like.
The invention also relates to a network using the packet transmitting apparatus as a node.
The invention further relates to a packet transmitting method which is used in the network or node.
2. Description of Related Art
ATM (Asynchronous Transfer Mode) technique is being developed extensively.
As an example of literature regarding a conventional technique of this kind, the following literature is known.
“Easy to understand B-ISND technique”
(p. 143, compiled by The new ITU association of Japan, Inc.)
As described in this literature for example, even when a 53-byte cell complying with the ITU-T (International Telecommunications Union—Telecommunications Standardization Sector) recommendation is an idle cell which does not have valid user information in the payload field, the number of alternating times between “0” and “1” of each bit is equal to eight in a cell header and is equal to 288 (=6×48) in the payload field.
An ATM transmitting apparatus, such as a conventional ATM switchboard or the like, is shown in FIG.
1
. As shown in the figure, processes of an ATM layer such as cell processing units
3
to
5
are performed directly to all of ATM cells including idle cells.
When reading the ATM cell of (1 byte×53 bytes) in various transmitting apparatuses (nodes) of the ATM cells, the operation for sequentially reading the bits in each byte from one end to the other end and also reading the next one byte from one end to the other end is repetitively executed for the number of times corresponding to 53 bytes. In other words, when the ATM cells are serially read, even if a CMOS (complementary MOS) circuit whose electric power consumption is small is used, the larger the number of alternating times, the more the electric power consumed by circuits in the transmitting apparatus.
When the electric power consumption increases as mentioned above in each circuit in the transmitting apparatus, waste of the electric power in the whole transmitting apparatus becomes very large.
OBJECT AND SUMMARY OF THE INVENTION
In order to solve the problem, according to a first aspect of the invention, a packet transmitting method of processing a packet having a control information area and a user information area by a function block in a node. and, thereafter, transmitting the packet from the node comprises the following steps.
That is, (1) whether information in the user information area of the packet is useless for the user or not is discriminated on the basis of the information in the control information area or the user information area, (2) the packet judged useless is converted into a predetermined format in which the number of alternating times of a bit pattern has been reduced and the packet is allowed to pass through the function block, and (3) the bit pattern of the packet is returned to a state before the conversion at least before the packet is transmitted from the node.
According to a second aspect of the invention, a packet transmitting apparatus for processing a packet having a control information area and a user information area by a function block in a node and transmitting the packet from the node comprises:
discriminating means for discriminating whether information of the user information area in the packet is useless for the user or not on the basis of the information of the control information area or the user information area; first format converting means for converting the packet determined to be useless into a predetermined format in which the number of alternating times of a bit pattern has been reduced and allowing the packet to pass through the function block; and second format converting means for returning the bit pattern of the packet to a state before the conversion at least before the packet is transmitted from the node.
Furthermore, in a network according to a third aspect of the invention, the transmitting apparatus is used as a node.
REFERENCES:
patent: 5740158 (1998-04-01), Aoki et al.
patent: 6134249 (2000-10-01), Nakao
patent: 05-135187 (1993-01-01), None
patent: 06-030018 (1994-04-01), None
Eguchi Kohei
Ishiba Kazuo
Oki Electric Industry Co, Ltd.
Rabin & Berdo P.C.
Ton Dang
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