Multiplex communications – Duplex – Convertible to half duplex
Reexamination Certificate
2000-05-26
2004-10-12
Qureshi, Afsar M. (Department: 2667)
Multiplex communications
Duplex
Convertible to half duplex
C370S395400, C370S395620, C370S421000, C709S242000, C710S117000
Reexamination Certificate
active
06804205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method and apparatus for synchronization when signals in accordance with IEEE (Institute of Electrical and Electronics Engineers) 1394 are transmitted over a medium of half duplex transmission.
2. Description of the Background Art
Standards and draft standards such as high performance serial bus IEEE Std 1394-1995 (and P1394a and P1394b proposed as additional specification thereof) have been known as prior art techniques of this field. In such (draft) standards, nodes connected to a bus are synchronized by providing a packet for synchronization, which is called a cycle start packet, over the bus once at every 125 micro seconds.
The cycle start packets are transmitted by a node called a cycle master node, which has a cycle timer register serving as a reference for synchronization.
FIG. 1
represents a format of the cycle start packet. Referring to
FIG. 1
, a cycle start packet consists of a total of 160 bits.
FIG. 1
represents the 160 bits in the form of 32 bits×5 stages. The cycle start packet includes, in the order of transmission, the first field of 16 bits representing a packet destination nodes; the second field of 8 bits; the third field of 4 bits representing the type of the packet; the fourth field of 4 bits representing packet priority; the fifth field of 16 bits representing a transmission node; the sixth field of 48 bits representing a destination address; the seventh field of 32 bits representing a value of the cycle time register at the cycle master node at the time of packet transmission; and the eighth field of 32 bits storing a CRC (Cyclic Redundancy Check) code for validating whether the contents of the packet are correct.
The value of the first field is “FFFF” in hexadecimal notation, representing that the packet is a broadcast packet. The “broadcast packet” refers to a packet which is addressed to all the nodes connected to the bus.
The value stored in the second field is, for the cycle start packet, always “00” in hexadecimal notation.
The third field stores the value of “8” in hexadecimal notation (“1000” in binary notation) for the cycle start packet.
The value stored in the fourth field is, for the cycle start packet, always the value representing the highest priority (“FFFF” in hexadecimal notation).
The fifth field stores a value representing a transmission node of the cycle start packet.
The sixth field stores, for the cycle start packet, an address of the cycle timer register holding time information at each node (“FFFFF0000200” in hexadecimal notation).
The contents related to the value of the cycle time register stored in the seventh field will be described later.
FIG. 2
represents the configuration of the cycle time register described above. The cycle time register is a 32-bit register, which is used divided into “second_count” of 7 bits, “cycle_count” of 13 bits and “cycle_offset” of 12 bits.
“Second_count” is a field representing seconds, which is incremented by a carry of “cycle_count”, which will be described later.
“Cycle_count” is a field representing a number of cycles each equal to one 8000th of a second. This field is incremented by a carry of “cycle_offset”, which will be described later, and when the value of this field reaches 8000, it is carried up and reset to 0. When this field is reset, the value of “second_count” field is incremented.
“Cycle_offset” is a field representing an offset in a cycle counted at a clock of 24.576 MHz. This field is incremented by the clock of 24.576 MHz and when the value reaches 3072, it is carried up and reset to 0. When this field is reset, “cycle_count” field is incremented. The offset in the third field is delay information from the reference start time of the cycle.
Each node repeats all the packets including the received cycle start packet to ports other than a reception port, with an almost constant repeat delay time. Thus, the packets are transmitted to all the nodes. Each node updates contents of a cycle time register of the node itself, by the time information contained in the received cycle start packet. This enables synchronization of the entire bus. This will be described with reference to
FIGS. 3 and 4
.
In the following description, three nodes
100
a
(node A),
100
b
(node B) and
100
c
(node C) are daisy-chain-connected using an IEEE 1394 bus
101
, as shown in FIG.
3
. Internal configurations of the nodes are identical. Therefore, these nodes may sometimes be generally referred to a node
100
.
In the example shown in
FIG. 3
, it is assumed that node A is the cycle master node.
Referring to
FIG. 4
, each node
100
has a physical layer controller
110
and a link layer controller
120
. A node which performs a repeat process only, which will be described later, may have the physical layer controller only.
Physical layer controller
110
has at least one port
111
for exchanging data over bus
101
. Physical layer controller
110
includes a reception data bus
12
for propagating data received at port
111
, a transmission data bus
13
for propagating data to be transmitted from port
111
, a resynchronization unit
14
for synchronizing received data with a local clock, and a link layer I/F
15
which is an interface with link layer controller
120
.
Link layer controller
120
includes a cycle time register
121
, and a physical layer I/F
122
which is an interface with physical layer controller
110
.
In a state where the cycle start packet is to be transmitted, node A (
100
a
) as the cycle master node issues a transmission request to IEEE 1394 bus. When transmission is enabled, the cycle start packet including the contents of cycle time register
121
of node A (
100
a
) as the cycle master node is formed by link layer controller
120
, and transmitted through physical layer I/F
122
in link layer controller
120
, link layer
1
/F
15
in physical layer controller
110
, transmission data bus
13
and port
111
. Nothing is transmitted from port
111
which is not connected to anywhere.
Node B (
100
b
) connected to cycle master node (node A) by the IEEE 1394 bus applies the packet data received from port
111
through reception data bus
12
to resynchronization unit
14
. The received packet data is re-synchronized with the local clock of node B at resynchronization unit
14
, and transmitted through the transmission data bus
13
from port
111
other than the port which has received the data. This is the process referred to as “repeat.”
In parallel with the repeat process, node B (
100
b
) transmits the re-synchronized packet data to link layer controller
120
through link layer I/F
15
and physical layer I/F
122
. When the packet is the cycle start packet, a value of cycle time register
121
in link layer controller
120
is updated by the value of “cycle_time” field contained therein.
Node C (
100
c
) connected to node B (
100
b
) by the IEEE 1394 bus rewrites the value of cycle time register
121
in link layer controller
120
, by the value of the “cycle_time” field contained in the cycle start packet which has been re-synchronized with the local clock at node C (
100
c
), similar to node B (
100
b
). In the example of
FIG. 3
, there is not the port
111
which is connected to anywhere other than the port
111
which has received the data at node C, and therefore, repeat process does not take place.
By the above described operation, the three nodes (
100
a
,
100
b
and
100
c
) can be synchronized.
Though there are three nodes in the example of
FIG. 3
, larger number of nodes may be connected. Such an example may be considered as having a plurality of nodes corresponding to node B (
100
b
) connected in a longer daisy chain. Alternatively, or in addition, nodes corresponding to node A or node B may have a plurality of transmission destination (repeat destination) ports and in star connection.
Another prior art example includes an IEEE 1394 bridge connecting two IEEE 1394 buses, which is discussed for standardization by P1394.1, one of Standards Committees of IEEE.
Ichikawa Yuji
Nakano Daisuke
Nishimura Takashi
Sumi Kazuyuki
Ueda Toru
Birch & Stewart Kolasch & Birch, LLP
Qureshi Afsar M.
Sharp Kabushiki Kaisha
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