Television – Receiver circuitry
Reexamination Certificate
2006-05-16
2006-05-16
Natnael, Paulos M. (Department: 2614)
Television
Receiver circuitry
C345S520000
Reexamination Certificate
active
07046308
ABSTRACT:
A digital television/local bus interface logic supports handling of digital television (DTV) data with non-tearing. The interface logic provides a dual frame buffer DTV architecture in which a pair of DTV/local bus frame buffers alternate functions: one frame buffer stores incoming DTV data and the other frame buffer stores the outgoing DTV data. When a refresh of a display device reaches a programmed position of the display device, the interface logic determines which frame buffer is being updated by the incoming DTV data. The outgoing DTV data is then read from an opposite frame buffer and transmitted to the display device. The interface logic receives a horizontal sync signal and a vertical sync signal from the graphics controller for monitoring refresh of the display device. The interface logic also provides an architecture for transferring decoded DTV data over a local bus to the graphics controller.
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Dao Giang H.
Moriarty Michael P.
Tran Thanh T.
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