Method and apparatus for translating rectilinear information int

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340747, 340723, G06F 3153

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049454978

ABSTRACT:
A circuit which computes the scan position of any pixel on the display as the sum of the number of scan lines multiplied by the number of pixels per scan line plus the number of pixels on the scan line to the particular position using an adder for a changing portion of the computation and an incrementer for a constant portion of the computation and combining the two of these to produce a result which accomplishes in a relatively economic fashion what would normally require an inordinate number of gates to obtain a variety of screen resolutions which are not simply powers of two multiples of one another.

REFERENCES:
patent: 4020281 (1977-04-01), Davis, Jr.
patent: 4459676 (1984-07-01), Oguchi
patent: 4593372 (1986-06-01), Bandai et al.
patent: 4620288 (1986-10-01), Welmers
patent: 4790025 (1988-12-01), Inoue et al.
patent: 4827250 (1989-05-01), Stallkamp
patent: 4829446 (1989-05-01), Draney

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