Patent
1996-06-27
1999-05-11
Ellis, Richard L.
395568, G06F9/455
Patent
active
059037601
ABSTRACT:
A method for increasing the performance of binary translated conditional instructions. According to one embodiment of the invention, a conditional instruction compatible with the first ISA is decoded. The condition of the conditional instruction is dependent on at least on status flag. The conditional instruction is translated to be compatible with a second ISA, wherein the condition of the conditional instruction is altered to be dependent on a previously computed difference between two values, the difference residing in a memory location.
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Baraz Leonid
Farber Yaron
Ladiray Gallia
Levhari Yossi
Ellis Richard L.
Intel Corporation
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