Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1998-07-06
2000-12-19
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
709208, G06F 1516
Patent
active
061638358
ABSTRACT:
A method of transferring data between a slave device (20) in communication with a processor interface bus (34) where the processor interface bus is in communication with a master device (12) including receiving an address from the processor interface bus (34) where the address was provided by the master device (block 302). A first signal is asserted (blocks 318 and 324) on the processor interface bus (34) to indicate that the slave device (20) is servicing a data transfer transaction. A second signal is asserted (block 320) on the processor interface bus (34) to indicate whether data to be transferred using the processor interface bus (34) is to be stored in main memory (36) by a main memory controller (32) in communication with the processor interface bus (34). The data is transferred (block 326) between the slave device (20) and the processor interface bus (34).
REFERENCES:
patent: 5528764 (1996-06-01), Heil
patent: 5790831 (1998-08-01), Lin
patent: 5799161 (1998-08-01), Merrick
patent: 5870568 (1999-02-01), Culley
patent: 5884027 (1999-03-01), Garbus
Intel Corp. 1996, Pentium Pro Family Developer's Manual, vol. 1: Specfications, Section 4.3.1. Bus Protocol pp. 4-21--4-32.
Motorola Inc. 1997, MPC106 PCI Bridge/Memory Controller User's Manual, Section 4.4.5 60x Local Bus Slave Support, pp. 4-21--4-22.
Motorola Inc. 1995, MPC105 PCII Bridge/Memory Controller User's Manual, Section 4.4.5. 60x Bus Slave Support, pp. 4-21--4-22.
Digital Equipment Corp. 1997, Digital Semiconductor Alpha 21164PC Microprocessor Hardware Reference Manual, Order #EC-R2W0A-TE, http://www.digital.com/semiconductor, pp. 3-1--4-60.
David M. Fenwick et al., Digital Technical Journal 1995, The AlphaServer 8000 Series: High-end Server Platform Development, vol. 7, No. 1, pp. 43-63.
Sun Microelectronics Jul. 1997, STP1-31, UltraSPARC.TM.-ll, Data Sheet: Second Generation SPARC v9 64-Bit Microprocessor With VIS, pp. 1-41.
Integrated Device Technology Feb. 1996, IDT R5000.TM.RISC Microprocessor, Processor Bus interface Reference Manual, Version 10, pp. 1-1--4-39.
William R. Bryg, et al. Hewlett-Packard Journal Feb. 1996, A High-Performance, Low-Cost Multiprocessor Bus for Workstations and Midrange Servers, pp. 1-7.
Hewlett-Packarg Journal Feb. 1996, Runway bus Electrical Design Considerations, pp. 1-3.
Advanced Micro Devices, Inc. (AMD), Section 4 Logic Symbol Diagram and Selection 5 Signal Descriptions, pp. 5-1--6-45.
Intel, Pentium.TM.pro processor with 1 mg L2 Cache at 200 MHZ, Appendix a signal listing, pp. 60-76.
Intel, Pentium.TM.Processor at 233 MHZ, 266 MHZ, 300 MHZ and 333 MHZ, Appendix A, pp. 83-90.
Garcia Michael Julio
Reynolds Brian Keith
Snyder Michael Dean
Todd David William
Coleman Eric
Gariazzo Joanna P.
Motorola Inc.
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