Method and apparatus for transferring data between a host proces

Details Method and apparatus for transferring data between a host proces Method and apparatus for transferring data between a host proces

1986-10-20

1988-05-17

Atkinson, Charles E.

Excavating

364200, G06F 1110

Patent

active

047456043

ABSTRACT:
In a data processing system in which two-level error correction is performed on variable length data being transferred between the host processor and the data storage device, the logical length of the data being transferred is computed during a fixed time gap with computation continuing after termination of the fixed time gap and commencement of the data transfer. The computation required for the logical length of the data field to accommodate two-level ECC is accomplished by first comparing the actual field length with a value predetermined by the subblock length of the two-level ECC. If the actual length is greater than the predetermined value, then a value equal to the subblock length plus first level ECC bytes is loaded into a counter which begins decrementing at the termination of the fixed time gap so as to synhronize by the byte-by-byte transfer of the data. As the data is being transferred the computation continues. When the computation has been completed, a value equal to the difference between the computed logical length and the subblock length plus first level ECC bytes is loaded into other counters which begin decrementing when the first counter reaches zero. In this manner transfer of the data is not interrupted. This permits two-level ECC to be incorporated into prior data processing systems which utilize a conventional track format with predetermined fixed time gaps, even though such fixed time gaps would otherwise be of insufficient duration to permit computation of the logical length required for two-level ECC.

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J. S. Conzola et al., "Error Correction Without Speed Degradation", IBM Technical Disclosure Bulletin, vol. 10, No. 8, (Jan. 1968), p. 1275.

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