Method and apparatus for tracing multiple errors in a computer s

Details Method and apparatus for tracing multiple errors in a computer s Method and apparatus for tracing multiple errors in a computer s

1992-09-29

1995-08-22

Beausoliel, Jr., Robert W.

Excavating

371 51, 371 48, 395550, 39520001, 39518306, 3951831, G06F 1100

Patent

active

054448590

ABSTRACT:
An approach to error assessment in computer systems is based on storing important state information while the machine is operating in a trace memory for each cycle of the clock. The trace memory is then coupled through the scan interface or otherwise to the service processor for use in analyzing the error. A set of signal lines in the data processing system is connected in parallel to the input port of the trace memory. Storing logic is coupled to the processor clock and to the input port of the memory, for storing information from the set of signal lines in successive locations in the trace memory in response to successive cycles of the clock. The output port of the trace memory is coupled to the service processor. The system also includes logic which counts the number of cycles of the clock after detection of an error until stopping of the clock and a system for tagging storage locations in the trace memory that correspond to cycles in which an error was detected.

REFERENCES:
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patent: 4924466 (1990-05-01), Gregor et al.
patent: 5220567 (1991-12-01), Dooley et al.
patent: 5251227 (1993-10-01), Bruckert et al.

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