Dynamic information storage or retrieval – Information location or remote operator actuated control – Selective addressing of storage medium
Reexamination Certificate
1997-10-21
2001-01-09
Neyzari, Ali (Department: 2752)
Dynamic information storage or retrieval
Information location or remote operator actuated control
Selective addressing of storage medium
C369S059160, C369S275300
Reexamination Certificate
active
06172947
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for recording a data signal containing a synchronous signal on a rewritable recording medium such as a phase-changing optical disk and an apparatus for recording and reproducing a data signal on and from the rewritable recording medium such as a phase-changing optical disk.
2. Description of the Related Art
There has been proposed a phase-changing optical disk as one of high-density recording mediums for repetitively rewriting data. The description will be oriented to the concrete technology of recording and reproducing a signal on and from this type of phase-changing optical disk.
FIG. 1
schematically illustrates a sector format of a data signal to be recorded on the phase-changing optical disk that is an example of a rewritable recording medium.
The data signal shown in FIG. l is recorded on sectors of an address area pre-formatted when manufacturing the optical disk. The address area contains the data indicating a physical address on the disk. When recording the data, the operation is executed to read the address signal recorded on this address area for accessing a target address and then to record the data signal formatted as shown in
FIG. 1
on the timing based on the reproduction signal of the address area if the target address is reached.
In this data signal format, a predetermined continuous repetitive pattern called VFO is recorded at the head of the format. This VFO is a pattern on which the data signal can be reliably reproduced by varying an oscillation frequency of a phase locked loop (PLL) in reproducing the data signal. Hence, if the number of revolutions of the disk is variable, the data pattern allows the data signal to reliably be reproduced. The pattern contains many pieces of edge information, that is, short repetitive intervals, because the existence of many pieces of edge information is likely to execute the PLL pull-in operation with respect to this pattern.
An SYNC (synchronous pattern) following the VFO is a pattern used as a synchronous signal of the data area and utilizes a pattern that does not normally appear in the data. A DATA recorded after the SYNC indicates data containing data used by a user and additional information such as an ECC (error correcting code), control data, and RESYNC (resynchronous pattern).
FIG. 2
is a block diagram showing an example of a basic arrangement of a recording system provided in a general apparatus for recording and reproducing a signal.
In operation, when a pre-pit (pre-format) address pre-recorded and pre-formed on the disk is correctly detected, a timing generator
11
of a reproduction system operates to output an ID detection signal and initialize a timing generator
13
of a recording system. The recording system is controlled on various kinds of timings generated by the timing generator
13
so that the recording system can perform a recording operation according to a predetermined recording format.
Concretely, the timing generator
13
operates to supply various timing signals to a control unit (not shown), a selecting circuit
17
, and a parallel/serial converter
18
and generate a recording gate (to be discussed below). This recording gate is a signal for limiting the recording range of the data on a time axis.
The selecting circuit
17
is inputted with the data from the control unit (not shown) through an interface unit
14
and with a SYNC pattern from a SYNC pattern generator
15
and a VFO pattern from a VFO pattern generator
16
. The selecting circuit
17
operates to select one of these signals based on the timing signal sent from the timing generator
13
and supply it to the parallel/serial converter
18
.
The parallel/serial converter
18
operates to parallel-to-serial convert the output from the selecting circuit
17
according to the output from the timing generator
13
and output the converted signal as recording data according to the format shown in FIG.
1
.
The timing generator
11
of the reproduction system is inputted with the reproduction clock and the timing generator
13
of the recording system is inputted with the recording clock.
FIG. 3
is a block diagram showing an example of a basic arrangement of a reproduction system included in the conventional apparatus for recording and reproducing a signal, which corresponds to the recording system of the apparatus illustrated in FIG.
2
. The components of
FIG. 3
that are common to those of
FIG. 2
have the same reference numbers as those of FIG.
2
.
The reproduction system operates to detect any sector mark or a pre-pit address pre-recorded and pre-formed on a disk with an embossing technique for the purpose of predicting the location of the VFO or detect a reproduction RF signal for specifying the location of the VFO and to activate a phase-locked loop to pull the phase of the reproduction RF signal of the VFO. The timing generator of the reproducing system is initialized by detecting the pre-pit address (ID signal) pre-recorded and pre-formed on the disk and then is operated to predict the location of the SYNC and generate a SYNC detecting window signal. Then, if the SYNC is detected in the SYNC detecting window signal, the timing generator determines the synchronization is obtained and initializes the timing generator of the reproduction system for controlling the reproduction system. This timing generator of the reproduction system controls demodulation of data, serial/parallel conversion, interface with the control unit (not shown), and the like.
By detecting the reproduction RF signal, the location of the VFO is specified. Then, the PLL is activated for the reproduction RF signal of the VFO for detecting the SYNC after the VFO. Then, the detected SYNC pattern is used as a synchronous pattern.
In the operation of the reproduction system, when the PLL is locked to the VFO, the data is taken out of the reproduction RF signal for synchronous pull-in and data demodulation based on the detected SYNC. After the reproduction clock is extracted, the data reproduction is executed by using the reproduction clock.
Concretely, between when the reproduction is started and when the reproduction RF signal of the VFO is detected, the PLL is activated for the predetermined fixed pattern supplied from a fixed pattern generator
22
with, e.g., a crystal oscillator so that an internal clock is pre-oscillated at a frequency closing to a target.
When the reproduction RF signal of the VFO is detected, the PLL is activated for the reproduction RF signal for synchronously pulling the signal at fast speed. After the signal is pulled, it is effective to lower the gain of the PLL circuit, thereby reducing the possibility of unlocking the phase of the signal.
The reproduction RF signal read from the disk is subject to amplification and equalization through the effect of the RF reproducing unit
20
. The processed signal is supplied to a RF detector
21
and a binary circuit
23
.
The RF detector
21
operates to detect a RF reproduction signal of the VFO and supply the signal to the flip-flop
24
as a reset input. The binary circuit
23
operates to digitize the RF reproduction signal and supply it to a selecting circuit
25
and a data extracting unit
27
.
The flip-flop
24
is inputted with the signal supplied from the RF detector
21
as a reset input and with the timing signal of the reproduction system supplied from the timing generator
13
of the recording system as a set input. When the RF detector
21
detects the reproduction RF signal, the flip-flop
24
is set. The output of the flip-flop
24
is supplied as a selecting signal to the selecting circuit
25
.
The selecting circuit
25
is inputted with the output of a fixed pattern generator
22
and the output of the binary circuit
23
. The selecting circuit
25
selects one of the inputs according to the selecting signal supplied from the flip-flop
24
and then supplies it to a PLL circuit
26
.
The PLL circuit
26
operates to pull in the digitized RF reproduction signal supplied throug
Frommer William S.
Frommer & Lawrence & Haug LLP
Neyzari Ali
Sony Corporation
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