Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant
Reexamination Certificate
2001-09-26
2003-09-16
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With specified dopant
C257S327000, C257S328000, C257S335000, C257S358000, C257S359000, C257S360000, C257S336000, C257S344000, C257S408000, C257S608000
Reexamination Certificate
active
06621146
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits and, more particularly, to linearization of the transconductance of active devices in integrated circuits.
BACKGROUND OF THE INVENTION
In semiconductor integrated circuits it is occasionally desirable to place a resistance in series with the source or drain of field effect devices, such as metal oxide semiconductor field effect transistors (MOSFETs). A series source resistance accomplishes device degeneration with improved transconductance linearity or superior matching to other similarly degenerated devices. A series drain resistance provides precision gain and stabilizes output conductance in current steering circuits. Series resistances in both terminals offer a symmetrical device that can isolate capacitances in switching applications and provide a precision gain block.
For example, series source resistances are often used in precision current mirrors, where the drain current in a reference transistor is mirrored into the drain of one or more output transistors at a desired current gain. The desired current gain can be accomplished by scaling the sizes of the output transistors relative to the size of the reference transistor or by scaling the relative sizes of resistors placed in series with the transistors. For example, a gain of two can be accomplished by making the output transistors twice the size of the reference transistor. Alternatively, a gain of two can be accomplished by placing a resistance of “R” in series with the reference transistor and a resistance of “R/2” in series with the output transistors.
Scaling the sizes of the transistors themselves can be difficult to control precisely and is usually accomplished by increasing the device area. With series resistances the level of current through each transistor becomes more a function of the series resistance than a function of the transistor size, therefore allowing more accurate control of the current gain in a current mirror. Also, the output impedance is increased which makes the current mirror less sensitive to external effects.
The standard approach for introducing a series resistance in a semiconductor device is to use a separate mask-defined diffused, thin-film or implanted resistor, which is electrically coupled to special contacts at the local interconnect layer. These contacts are then electrically coupled in series with the source or drain contacts of the semiconductor device.
This type of series resistance has several disadvantages. For example, the resistance consumes considerable area on the integrated circuit and introduces variability in current gain due to variability in local contact resistance. Precision current mirroring is particularly difficult in scaled-down semiconductor technologies having low rail voltages. Also, short channel active devices can often have poorly matched device characteristics. Improved matching has always come at the expense of increased area.
Improved methods and structures for linearizing and matching semiconductor transistors are therefore desired.
SUMMARY OF THE INVENTION
One aspect of the present invention relates to an integrated circuit having a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.
Another aspect of the present invention relates to an integrated circuit having first and second voltage supply terminals for providing a supply voltage, a substrate, and a degenerated transistor coupled between the first and second voltage supply terminals. The degenerated transistor includes a gate, heavily-doped source and drain regions embedded in the substrat, source and drain contacts positioned on the source and drain regions, respectively, a channel defined beneath the gate and between the source and drain regions, and a lightly-doped region positioned between a respective one of the source and drain regions and the channel. The lightly-doped region has a length measured from the channel to the respective source or drain region and a width measured along a width of the gate that are selected such that the lightly-doped region produces a voltage drop from the respective source or drain contact to the channel of at least one percent of the supply voltage.
Another aspect of the present invention relates to a current mirror fabricated on an integrated circuit. The current mirror includes a current input, a current output, and first and second transistors. The first transistor includes a first gate, a first heavily-doped source region, a first source contact, a first heavily-doped drain region, a first drain contact electrically coupled to the first gate, a first channel, and a first lightly-doped source region which extends between the first channel and the first heavily-doped source region. The first lightly-doped source region extends for a first length that is selected such that the first source contact is spaced from a respective edge of the first gate by a first distance that is greater than a minimum distance defined for the technology in which the integrated circuit is fabricated and the first lightly-doped source region has a desired first resistance in series with the first source contact. The second transistor includes a second gate electrically coupled to the first gate, a second heavily-doped source region, a second source contact, a second heavily-doped drain region, a second drain contact that defines the current output, a second channel, and a second lightly-doped source region which extends between the second channel and the second heavily-doped source region. The second lightly-doped source region extends for a second length that is selected such that the second source contact is spaced from a respective edge of the second gate by a second distance that is greater than the minimum distance and the second lightly-doped source region has a desired second resistance in series with the second source contact.
Another aspect of the present invention relates to a method of fabricating transistors on a substrate for a given semiconductor technology. The method includes fabricating the transistors with a control terminal, first and second output terminals, a channel, first and second heavily-doped regions in contact with the first and second output terminals, respectively, on opposing sides of the channel, and a lightly-doped region extending between the first heavily-doped region and the channel. A first set of the transistors is fabricated such that the lightly-doped region of each transistor in the first set has a first length between the first heavily-doped region and the channel and such that the first output terminal has a standard spacing from a nearest edge of the control terminal of that transistor. At least one of the transistors not in the first set is degenerated such that the lightly-doped region of the degenerated transistor has a second length, which is greater than the first length, between the first heavily-doped region and the channel and such that the first output terminal of the degenerated transistor has a non-standard spacing, which is at least twice the standard spacing, from a nearest edge of the control terminal of the degenerated transistor.
REFERENCES:
patent: 4199733 (1980-04-01), Schade, Jr.
patent: 4978628 (1990-12-01), Rosenthal
pate
LSI Logic Corporation
Soward Ida M.
Westman Champlin & Kelly
Zarabian Amir
LandOfFree
Method and apparatus for the use of embedded resistance to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for the use of embedded resistance to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for the use of embedded resistance to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3019560