Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Forming lateral transistor structure
Reexamination Certificate
1999-06-16
2001-09-04
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Forming lateral transistor structure
C438S340000, C438S525000, C438S558000
Reexamination Certificate
active
06284615
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for the selective doping of a wafer of semiconductor material by ion implantation, which can advantageously be used in the manufacture of integrated circuits having components with good dynamic performance.
BACKGROUND OF THE INVENTION
Electronic devices with good dynamic performance, that is, devices with a high frequency or a high switching speed, usually have extremely small dimensions and very thin junctions. The double polysilicon self-aligned technique (or DPSA), which can produce vertical npn bipolar transistors with transition frequencies greater than 50 GHz by virtue of regions with very small vertical doping profiles and by virtue of the use of lithographic processes which can produce sub-micrometric geometrical arrangements, is known. An application of this technique which is described in the Applicant's European patent application EP 0709896 also enables lateral pnp bipolar transistors to be produced with a single additional step; although these lateral pnp bipolar transistors do not have dynamic performance comparable with that of the vertical npn transistors, they are suitable or use to form, for example, biasing circuits, current mirrors, and load devices for gain stages in the same integrated circuit, in combination with vertical npn transistors.
An additional step is required which includes a photolithographic process for forming a mask which screens the base channels of the lateral pnp transistors during the ion implantation which is necessary to form the intrinsic base regions of the vertical npn transistors.
In view of the fact that any step of a method for manufacturing an integrated circuit involves manipulations and contaminations of various kinds which reduce the final output of the method, the object of the present invention is to propose a method of doping by implantation in which it is possible avoid the use of a mask as an implantation screen.
SUMMARY OF THE INVENTION
According to principles of the present invention, a method and apparatus are provided for selective doping of a wafer of semiconductor material. A screening layer is formed at a desired location on the wafer during the process steps. An opening is formed in the screening layer of a selected width. An ion implantation is performed into the opening at a selected angle relative to the perpendicular. The angle is selected so as to strike the opening from a first side. A second ion beam is formed which strikes the opening from a second, opposite side. The thickness of the layer, and the width of the opening, together with the angles of inclination are selected such that the beams strike the base to provide a substantial uniform doping of the wafer within a selected region. According to other principles of the present invention, a second opening is formed in the screening layer which is more narrow than the first opening. The second opening is sufficiently thin that the same ion beams, when directed at the wafer through the second opening, do not strike the bottom of the opening so that no ion implantation occurs into the semiconductor substrate under the second opening.
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Palara Sergio
Pinto Angelo
Galanthay Theodore E.
Mulpuri Savitri
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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