Method and apparatus for the reduction of time interval error in

Details Method and apparatus for the reduction of time interval error in Method and apparatus for the reduction of time interval error in

1993-12-09

1995-10-10

Lee, Benny

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331 14, 327141, 327159, 327156, H03L 700

Patent

active

054574285

ABSTRACT:
A phase-locked loop circuit which utilizes multiple reference signals is formed with control circuitry to minimize time interval error. The phase-locked loop (PLL) comprises a switching device, phase detector, loop filter governable oscillator, frequency divider, signal sensing circuit and a TIE reduction control circuit. The PLL maintains a substantially constant .pi./2 radians between a first reference signal and its phase-locked output. Upon loss of the first reference signal, the signal sensing circuit causes the switching device to switch to a second reference signal. The second reference signal is of the same frequency but unknown phase relationship with the interrupted first reference signal. Upon switch over, the TIE reduction control circuit causes the frequency divider output to be interrupted and forced high for a quarter-cycle of the period of the reference signals to force the PLL to phase-lock on the second reference signal with minimal TIE.

REFERENCES:
patent: 4817199 (1989-03-01), Wallraff
patent: 4864253 (1989-09-01), Zwack
patent: 4972442 (1990-11-01), Steierman
patent: 4980899 (1990-12-01), Troost et al.
patent: 5059925 (1991-10-01), Weisbloom
patent: 5140284 (1992-08-01), Petersson et al.
patent: 5202906 (1993-04-01), Saito et al.
CCITT Draft Recommendation G.81s, Document No. DE/TM-3017-5, pp. 1-8, the publication date of this document is not readily available to the applicants.

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