Method and apparatus for the protection of sensitive data...

Static information storage and retrieval – Powering – Data preservation

Reexamination Certificate

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C365S189080, C365S226000

Reexamination Certificate

active

11234595

ABSTRACT:
Methods and apparatus for the protection of memory within an integrated circuit (IC) are provided for various phases of operation of the IC. Various portions of sensitive data may be contained within battery backed random access memory (RAM) (310), which may then be protected using either a passive, or an active, zeroization sequence depending upon the phase of operation of the IC. In an idle state, detection circuit (324) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312and314). In a configuration state, detection circuit (402) or (504) senses a drop in battery power (VBATT) to launch active destruction of RAM (310) memory using active zeroization circuits (312and314). In an operational state, various methods may be employed to detect and counteract the unauthorized access to RAM (310).

REFERENCES:
patent: 5581198 (1996-12-01), Trimberger
patent: 5844844 (1998-12-01), Bauer et al.
patent: 6357037 (2002-03-01), Burnham et al.

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