Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-01-28
2004-01-06
Niebling, John E. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000
Reexamination Certificate
active
06673638
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to producing process adjustably sensitive lithographic features on semiconductor wafers. More particularly, the present invention provides apparatus and methods using wavefront engineering to produce targets on semiconductor wafers which are sensitive to focus and dosage variations in equipment effectuating the printing of layers on wafers.
Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds and increased yield (numbers of usable chips produced from a standard semiconductor wafer). It is desirable to produce wafers with consistent dimensions, particularly as to the line widths printed on the devices. However, with smaller devices (where the critical dimension of the printed features are smaller than the exposure wavelength) the difficulty in meeting critical dimension tolerances increases. Certain wave front engineering techniques such as optical proximity correction (OPC) and phase shift mask (PSM) techniques are often applied to reticles to improve lithographic performance and extend the useful lifetime of optical exposure tools. The changes produced by these techniques are referred to as wavefront engineering features. Phase shift mask (PSM) techniques (strong-alternating, weak-embedded, and attenuating) are used mainly to improve lithographic resolution, improve depth of focus, and monitor the lithographic stepper or scanner performance using focus monitors. Optical proximity correction is a wavefront engineering technique wherein a modification of the photomask pattern (binary changes, i.e., adding or subtracting chrome on the mask) is made to compensate for changes in feature shape and size that occur during pattern transfer from the mask to the wafer. These feature changes may be caused by extra exposure due to the presence of adjacent lithographic features, a limitation in the wafer stepper/scanner, or a variation in the activity of a given wafer process step. OPC is also used on phase shifted masks to maximize the benefit gained from PSM technology. While OPC techniques are often used to correct for pattern fidelity error (a reduction in the quality of the aerial image) and improve process latitudes, OPC does little for improving resolution. In addition to OPC and PSM technologies, a variety of other wavefront engineering techniques are currently in use. For example, sub-resolution features called“scatter bars” (binary mask additions or sub-resolution mask patterns which do not print) improve lithographic behavior of small isolated and quasi-dense features by adjusting the shape of the aerial image—simply an extension of OPC technology.
Minor variations in process parameters, such as changes in focus and exposure dose on photolithographic exposure equipment (scanners/steppers), may cause the critical dimensions (CD) on the wafers to fall outside acceptable semiconductor manufacturing tolerances (typical CD specifications are +/−8%). A large number of process parameters may affect the dimensions of a resist pattern on a silicon wafer. Some of the most significant parameters include: resist thickness, focus position, exposure dose, resist pre and post bake temperatures and development temperature and time. While photolithographic exposure tools and photolithographic resist tracks continuously monitor and adjust for small fluctuating changes in the process conditions (bake times, exposure dose, focus, etc.,) the resulting resist feature size or critical dimension is a complex result of all process variables. Typically, semiconductor manufacturing facilities correct for process variation (drifting CD's) by adjusting only the exposure dose (e.g. hourly changes). This tends to provide the most economically viable solution.
Photolithography is one of the most important steps of the semiconductor manufacturing process. During the photolithographic process a semiconductor wafer is coated with a light sensitive material called a photoresist or resist (example; chemically amplified resist (CAR)) and is exposed with an actinic light source (excimer laser, mercury lamp, etc.,). The exposure light passes through a photomask and is imaged via projection optics onto the resist coated wafer forming a reduced image (typically 4× or 5× smaller) of the photomask in the photoresist. For positive chemically amplified resists (CARs) the actinic light source typically causes the production of photoacids that diffuse during post exposure bake and allow the resist to be rinsed away by an aqueous developer only in those regions receiving most of the exposure dose. Following the develop process the resist patterned wafers are sent to a metrology station to measure the critical dimensions or shape of the patterned resist features. Typical metrology tools include scatterometers, scanning electron microscopes and atomic force microscopes. The last step in the photolithographic process involves etching the resist-coated wafers using complex plasma chemistry to attack the semiconductor material not covered with photoresist.
Following etch, the resist coated wafers are cleaned and sent to a scanning electron microscope or other metrology for final lithographic inspection. Precise control of the printing process is necessary to ensure that the device line widths forming the pattern on the wafer fall within tolerance. Prior to etching, it is possible to repeat the lithographic processing if a problem is detected in time. After the photoresist wafers are physically etched it is too late to correct the photolithographic imaging process. Presently, one monitoring technique used is a lot sampling of the resist imaged wafers to determine if the line widths (critical dimensions) have fallen outside an acceptable range prior to etch. However, given the extremely small sizes of the devices, for example device sizes of 0.15 micron or smaller, expensive and slow metrology techniques are necessary. With these dimensions, one of the few effective tools currently in use to measure line widths is a scanning electron microscope (SEM). The wafers must be removed from their processing location and transported to the SEM. Moreover, the time required for SEM inspections is so extensive that a typical sampling rate may not detect a process drift until after a large number of wafers have been etched.
Other monitoring metrologies include; scatterometry techniques (ellipsometry, variable angle, reflection) using complex and expensive look-up libraries, and optical CD techniques utilizing an inexpensive optical metrology tool and dual toned line shortening (“schnitzl”) arrays to indirectly measure the critical dimensions of photoresist patterned wafers using line-end shortening techniques. While the OCD technique is fast and inexpensive the technique may or may not have the optimum process sensitivity that is required for day to day production monitoring routines. In practice the OCD technique can be used to determine both focus and exposure drifts by building a second order polynominal description of the complex CD drift with changes in focus and exposure. However, the ability to determine absolute direction of focus drifts requires the additional printing of test fields out of focus—which takes valuable exposure time and space on a semiconductor wafer.
What is needed is a quick and inexpensive method of detecting variations in the semiconductor process using optical metrology techniques that have adjustable levels of process sensitivity and are capable of predicting the direction of focus drifts.
SUMMARY OF THE INVENTION
To achieve the foregoing, and in accordance with the purpose of the present invention, a method for monitoring and controlling the photolithographic process parameters in a more versatile and effective way is described.
The present invention provides a method for controlling the variation in process parameters using modified target structures that have an adjustable degree of pro
Bendik Joseph J.
Hankinson Matt
Beyer Weaver & Thomas LLP
KLA-Tencor Corporation
Luk Olivia
Niebling John E.
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