Multiplex communications – Wide area network – Packet switching
Patent
1984-06-15
1986-06-24
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 17, H04J 116, H04J 314
Patent
active
045970726
DESCRIPTION:
BRIEF SUMMARY
The invention relates to a method for the examination of the internal interconnection system between n terminals of an electrical network and for storing the results of examination in a memory with n memory cells by means of measuring the existence or non-existence of signal passage between the terminals. The invention relates also to a method which can test an electrical network manufactured as a reproduction of a standard electrical network which has an interconnection system already examined and stored in a memory, such test including the indication of the differences between the tested and the standard networks. The invention relates to an apparatus for carrying out both kinds of method.
As it is widely known in the art in the field of manufacturing electrical networks with a large number of terminals the examination or control test of the interconnection system between the terminals is of outstanding significance.
In making such examinations information of "yes" or "no" type is required indicating whether there exists a connection between a tested pair of terminals or it is not existing. In general, the existence of a connection can be established if the electrical resistance between the terminals is below a threshold limit, and there is no connection, if the resistance is higher than the threshold limit.
Especialy in case of networks with large number of terminals (such as exceeding a couple of hundred or thousand terminals) the performance of such examinations is rather complicated and requires the usage of highly expensive machinery. The degree of complexity increases excessively with the number of terminals and the equipments designed for operating with smaller number of terminals can not be expanded due to theoretical considerations, because extending the number of terminals, certain inevitable additional problems will emerge. The main problem lies in that in the electrical network in principle an unlimited proportion of terminals can be galvanically interconnected to form a common point, and among the testing circuits connected to these terminals unwanted couplings and interactions might take place.
For the examination of networks with a large number of terminals computers are used due to the excessively large number of possible combinations, and the data defining the respective status conditions are stored in the memory of the computer. As far as we are informed, there have not been published any electronic means with self-programming performance which could automatically examine the internal structure of interconnections of an unknown electrical network.
The object of the invention is to provide a method and an apparatus for the examination and test of the internal interconnection system of an electrical network with a plurality of terminals which is capable of investigating the structure of interconnections of an unknown network by means of self-programming steps, which does not require complicated processor operations or even the usage of a processor and which has a minimized need for storage capacity that does not exceed the number of terminals of the network, i.e. in which the stored information has a minimum redundancy.
In a first aspect of the invention a method has been provided for the examination of an internal interconnection system between n terminals of an electrical network and for storing the results in a memory comprising n memory cells by means of measuring the existence or non-existence of the signal passage between the terminals, in which according to the invention the method comprises the steps of switching a marking state on the respective terminals by means of a demultiplexer with n outputs controlled by an address generator and searching the passage of the marking state by a multiplexer with n inputs connected to the terminals and being set by an other address generator, and in each stable state of the demultiplexer the throughpass of the marking state being searched according to steps of first cycles designated as cycles A, in each of said cycles A said multiplexer is st
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Galos Kalman
Somlai Lajos
Olms Douglas W.
Rokoff Kenneth I.
Vilati Villamos Automatika
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