Method and apparatus for the dynamic adjustment of data transfer

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Details

3642391, 3642403, 3642384, 3642716, 3649394, 36492793, 364DIG1, 395425, 395500, G06F 1314

Patent

active

052789748

ABSTRACT:
The bandwidth of a first bus and a second bus, unequal due to differences in protocol overheads and cycle times between the buses, are equalized without sacrificing any bandwidth on the lower bandwidth bus and without introducing any buffering in a control logic device. The control logic device equalizes the bandwidths of the buses by instructing a device coupled to the second bus to insert a partial dead bus cycle in a read transmission thereby dynamically adjusting read timing on the second bus when the second bus is heavily loaded.

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