Dynamic magnetic information storage or retrieval – Checking record characteristics or modifying recording...
Reexamination Certificate
1998-10-26
2001-04-17
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
Checking record characteristics or modifying recording...
C360S046000, C360S067000, C360S053000
Reexamination Certificate
active
06219192
ABSTRACT:
The present invention relates generally to a method of compensating for an additive signal in a data signal and circuitry for compensating for an additive signal in a data signal. The invention is particularly useful in a data channel employing partial-response maximum-likelihood (PRML) detection.
The method and apparatus have particular application to the compensation of transient signals produced on reading a data storage device with a magneto-resistive head due to thermal contact with asperities on the data storage medium.
Data storage units for computers consist of media on which data can be written, stored and read at a required time. Data is usually stored as magnetization patterns on the media, and these patterns are detected during a read process by a magneto-resistive (MR) head which produces a data signal A magneto-resistive (MR) head undergoes a change in resistance in the presence of a changing magnetic field, and this resistance change is transformed into an output voltage signal (data signal) by passing a constant current through the MR head. An example of such a data signal is illustrated in
FIG. 2
a,
which plots the magnitude of the data signal (measured in unspecified units) against time (measured in bit periods). MR heads are now becoming increasingly popular in magnetic data storage products such as the hard disk drive (HDD), due to the high signal to noise (SNR) and the robustness to tracking errors they provide. The output voltage signal from the MR head is amplified, and converted from an analogue signal to a digital signal. In products that use a partial-response-maximum-likelihood (PRML) channel the output voltage signal is passed through the PRML read channel to estimate the data that was recorded on the media. In a PRML read channel partial response (PR) signalling is used in combination with maximum-likelihood sequence detection (MLSD). The frequency response of the read channel is designed to have frequency nulls at dc and at the Nyquist frequency (half the data sampling frequency). This partial response format is achieved by the combination of an analogue filter, a variable gain amplifier (VGA), a sampling device and possibly a discrete-time filter. Maximum-likelihood sequence detection is achieved using a Viterbi detector. Further details of the application of a PRML system to digital magnetic recording may be found in “A PRML System for Digital Magnetic Recording”, IEEE Journal on Selected Areas in Communications, Vol 10, No 1, Jan. 1992, by Cideciyan et al.
FIG. 1
illustrates as a block diagram, a typical PRML write and read channel. A PRML channel refers to the circuitry that writes error control encoded data on to the media in the disk drive as magnetization patterns (write channel) and recovers the data stored on the medium, from the output voltage signals of the MR head in the head/disk block
104
(read channel).
For the write process, the error control encoded (ECC) data is passed to an encoder
101
for run-length limited (RLL) coding. The output of the encoder
101
is passed to a precoder
102
which is described by a 1/(
1⊕D
2
) operation, where D is the delay operator. The resulting bit pattern, output by the precoder
102
, is passed to the write pre-compensation circuit
103
which produces the final pulse signal to be applied to a write circuit incorporated in the head/disk block
104
. The write circuit provides a write current to produce the magnetization pattern on the media.
During the read out process, the signal from the MR head incorporated in the head/disk block
104
, is passed to a variable gain amplifier (VGA)
105
. The gain of the VGA
105
is controlled by a gain and timing control loop
107
. Slow variations in the data signal amplitude are compensated by the gain control loop
107
. The signal output from the VGA
105
is passed to a low-pass filter
106
. The output of low-pass filter
106
is input to the bit rate sampler
120
. The bit rate sampler
120
is connected to a voltage controlled oscillator (VCO)
110
which controls the sampling times of the bit rate sampler
120
. The VCO
110
is connected to and controlled by the gain and timing control loop
107
. The output of the bit rate sampler
120
is connected to an analogue to digital converter (ADC)
108
.The operational range of the ADC
108
(illustrated in
FIG. 2
a
) is not much larger than the nominal range of the data signal output from the low-pass filter
106
as can be seen from
FIG. 2
a.
The digitized samples, output from the ADC
108
, are applied to a discrete-time equalizer
109
, which is usually a finite impulse response (FIR) digital filter. The equalized samples, output from the discrete-time equalizer
109
is supplied as an input to the gain and timing control loop
107
and to the Viterbi detector
111
. The output of the Viterbi detector
111
is connected to a decoder
112
which run length decodes the output of the Viterbi detector to produce the error control encoded data originally supplied, during the write process, to the encoder
101
in the write channel.
The introduction of MR heads, along with the PRML read channel has been responsible for large improvements in magnetic data storage. However asperities or defects on the storage media, give rise to thermal effects in the MR head which tends to decrease the reliability of the MR head. These asperities or defects are referred to as thermal asperities. When an MR head hits a defect (asperity) on the disk, the friction between the MR head and the defect causes the temperature to rise sharply. This increases the resistance of the MR head element substantially, causing a voltage increase at the MR head output lasting for tens of nano-seconds. As the MR head element cools down to the temperature of the environment, the thermal asperity signal returns slowly to zero. The amplitude of the TA signal can be as high as 250% of the peak-to-peak data signal, and the time taken for the TA to decay to 30% of its maximum can be of the order of a few micro-seconds. This additive disturbance in voltage is called the thermal asperity (TA) signal. The MR head output saturates the ADC
108
used to convert the analogue output voltage signal to a digital signal. Thus at high data rates of the order of 100 MHz, the MR head output signal can exceed the operational range of the ADC
108
for a period spanning a few hundred bit periods causing long error bursts that the error correction techniques used cannot handle. The rise time of the TA signal is only of the order of a few bit periods. An example of a TA signal is illustrated in
FIG. 2
b.
In this Figure the magnitude of a TA signal (measured in unspecified units) is plotted against time (measured in bit periods). The MR head output is then a thermal asperity affected signal consisting of the additive combination of the data signal (
FIG. 2
a
) and a thermal asperity signal (
FIG. 2
b
). An example of a thermal asperity (TA) affected signal is illustrated in
FIG. 2
c.
In this Figure the magnitude of the TA-affected signal (measured in unspecified units) is plotted against time (measured in bit periods).
One way of reducing the effects of thermal asperity is to design heads that have reduced TA sensitivity. Two such heads are the flux guide head and the dual stripe head. The former lowers head sensitivity and the latter adds cost and complexity to the head.
Electronic compensation methods to take into account the TA error have been proposed. One class of prior arrangements (U.S. Pat. No. 4,914,398 and U.S. Pat. No. 5,057,785) for electronic TA abatement reconstructs the TA signal through envelope detection of the TA-affected signal and the subtraction of the envelope from the TA-affected signal, thereby restoring an approximation of the data signal. The method suffers from the disadvantage that the reconstruction circuitry adds to the complexity and introduces some delay. More importantly, the reconstruction is never perfect, and some data ripple and noise filter through, causing channel degradation. This degradation may not be notice
Gopalaswamy Srinivasan
Lee Yuan Xing
Liu Bin
Cooper & Dunham LLP
Data Storage Institute
Faber Alan T.
White John P.
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