Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-09-28
2004-10-12
Rao, Seema S. (Department: 2666)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395100, C370S419000, C370S463000, C370S474000
Reexamination Certificate
active
06804242
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to communications systems and, more particularly, to a method and apparatus for the channelization of cell or packet traffic over standard pc-buses.
2. Description of the Related Art
Packet switching communications networks, such as asynchronous transfer mode (ATM) communication networks, are typically made up of a number of communication nodes coupled for communication over a set of high speed communication links. Such a communication network usually enables communication among a wide variety of communication devices, including video, voice, data and facsimile devices. The topology of such a communication network typically enables a variety of communication paths be established between any two communication nodes in the network. Such communication paths are generally referred to as a virtual circuit in the communication network. Typically, a physical path though the communication nodes for such a virtual circuit is established according to bandwidth utilization requirements for the virtual circuit and the available resources in the communication nodes and on the high speed communication links.
In an implementation where ATM is used in conjunction with a computer, the ATM communication functions are typically incorporated entirely in hardware in a network interface circuit. Hardware implementations are sometimes costly due to the number of specialized components required and the relative rigidity of the design. To reduce costs, industry groups have suggested implementing host-based software protocol stacks under the control of an operating system, such as the Windows® operating systems sold by Microsoft Corporation. A software solution is inherently more flexible than a hardware implementation, and also, due to the lesser number of hardware components, reduces cost. A software installation base is normally more easily maintained and upgraded than a similar hardware base.
A software implementation, however, has certain limitations. For instance, a hardware interface having limited-size transmit and receive queues (e.g., first-in-first-out buffers {FIFOs}) is still required. ATM information is transferred in 53 byte packets or cells. Each cell includes a 5-byte header and a 48-byte body. Because the operating system is not real-time, latencies could occur that result in the receive buffer reaching its storage capacity, a situation that is especially damaging during time-critical data streams, such as voice or video traffic. Such latencies could result in losing the ATM connection. Also, the received cells must be transferred from the hardware interface across a system bus, e.g., a peripheral component interconnect (PCI) bus, so that the cells can be processed by the software layer. Because, ATM protocols are often used for high-bandwidth applications, the amount of traffic on the bus may be appreciable. Increased bus traffic increases the overall latencies of the end system (i.e., the computer), which could compound the problem associated with the limited-size receive buffer. Increased system latency also decreases the efficiency at which other processes executing on the end system may complete.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a computer system including an end system, a bus, a communications interface, and a bus controller. The bus is coupled to the end system. The communications interface is coupled to the bus and includes a physical layer, a receive buffer, and a channel control unit. The physical layer is adapted to receive an input signal and demodulate the input signal to generate a plurality of cells. The receive buffer is adapted to receive the cells. The channel control unit is adapted to identify cells in the receive buffer associated with the virtual circuits. The bus controller is coupled to the bus and is adapted transfer at least the cells associated with the virtual circuits over the bus to the end system.
Another aspect of the present invention is seen in a method for reducing traffic on a bus coupling an end system to an interface. A plurality of virtual circuits are maintained in the end system. An input signal is received. The input signal is demodulated to generate a plurality of cells. Cells associated with the virtual circuits are identified. At least the cells associated with the viral circuits are transferred over the bus to the end system after the cells have been identified as being associated with the virtual circuits.
REFERENCES:
patent: 5528763 (1996-06-01), Serpanos
patent: 5583863 (1996-12-01), Darr et al.
patent: 5946312 (1999-08-01), Suzuki
patent: 5999518 (1999-12-01), Nattkemper et al.
patent: 5999980 (1999-12-01), Tanaka et al.
patent: 6377583 (2002-04-01), Lyles et al.
patent: 6449252 (2002-09-01), Marsteiner
patent: 2303521 (1997-02-01), None
patent: WO 95/30318 (1995-11-01), None
Advanced Mircro Devices, Inc.
Palmehra Inder
Rao Seema S.
Williams Morgan & Amerson
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