Electrical computers and digital processing systems: multicomput – Network computer configuring – Reconfiguring
Reexamination Certificate
2000-12-29
2001-11-06
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: multicomput
Network computer configuring
Reconfiguring
C710S008000
Reexamination Certificate
active
06314461
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data communications and more particularly to the addition and subtraction of nodes to a common interconnect.
BACKGROUND OF THE INVENTION
Digital electronic systems such as computer systems often use a common interconnect to share information between components of the digital electronic system. For computer systems, the interconnect is typically the computer bus.
One type of system interconnect is described by IEEE Standards document P1394, Draft 7.1v1, entitled
IEEE Standard for a High Performance Serial Bus
(hereafter the “P1394 serial bus standard”). A typical serial bus having the P1394 standard architecture is comprised of a multiplicity of nodes that are interconnected via point-to-point links such as cables that each connect a single node of the serial bus to another node of the serial bus. Data packets are propagated throughout the serial bus using a number of point-to-point transactions, wherein a node that receives a packet from another node via a first point-to-point link retransmits the received packet via other point-to-point links. A tree network configuration and associated packet handling protocol ensures that each node receives every packet once.
The P1394 serial bus standard provides for an arbitrary bus topology wherein the hierarchical relationship between nodes of the serial bus is determined by the manner in which the nodes are connected to one another. A P1394 serial bus is configured in three phases: bus initialization, tree identification, and self identification. During bus initialization, the general topology information of the serial bus is identified according to a tree metaphor. For example, each node is identified as being either a “branch” having more than one directly connected neighbor node or a “leaf” having only one neighbor node. During tree identification, hierarchical relationships are established between the nodes. For example, one node is designated a “root” node, and the hierarchy of the remaining nodes is established with respect to the relative nearness of a node to the root node. Given two nodes that are connected to one another, the node connected closer to the root is the “parent” node, and the node connected farther from the root is the “child.” Nodes connected to the root are children of the root. During self identification, each node is assigned a bus address and a topology map may be built for the serial bus.
According to the P1394 serial bus standard, reconfiguration of a serial bus is required when either 1) a new node is joined to the serial bus, or 2) an identified node of the serial bus is removed from the serial bus. Reconfiguration is required to better ensure that all nodes of the serial bus are notified of the newly connected or disconnected node and that each node has a unique bus address. Typically, the node of the serial bus that detects a new connection or disconnection forces the three phase configuration to be performed by asserting a bus reset signal. The three phase configuration process typically requires several hundred microseconds to perform, during which time communications of data between nodes is halted. Such long periods of interruption may significantly affect the operation of the system for some uses of the serial bus. Therefore, it would be desirable to provide a mechanism that allows the connection and disconnection of nodes from the serial bus such that interruptions to serial bus traffic are reduced.
SUMMARY OF THE INVENTION
An electronic system interconnect is described that comprises a first node and a second node coupled to the first node and that allows for the addition of nodes to the interconnect after the interconnect is initially configured. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal. According to one embodiment, the electronic system interconnect is a serial bus, and the first node signals the addition of the third node after arbitrating for the serial bus. The use of normal bus arbitration to signal the addition of nodes to the serial bus reduces interruptions of bus traffic.
A method for building a topology map of a serial bus without requiring a bus reset is also disclosed. A bus topology manager node of the serial bus transmits a SEND_SELF_ID packet to a first node. The first node receives the SEND_SELF_ID packet and responds by transmitting a SELF_ID packet of the first node to the bus topology manager node. A parent node of the first node responds to the SELF_ID packet of the first node by transmitting its own SELF_ID packet. The bus topology manager node is thus able to build a bus topology map without requiring a bus reset.
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Duckwall William S.
Teener Michael D.
Apple Computer Inc.
Blakely & Sokoloff, Taylor & Zafman
Donaghue Larry D.
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